Added some more spi placeholder code

examples/spi/spi.code-workspace

@@ -1,10 +1,10 @@
 {
 	"folders": [
 		{
-			"path": "../.."
+			"path": "."
 		},
 		{
-			"path": "."
+			"path": "../.."
 		},
 		{
 			"path": "../../../drone-stm32-map"

examples/spi/src/tasks/root.rs

@@ -2,6 +2,21 @@
 
 use crate::{thr, thr::ThrsInit, Regs};
 use drone_cortexm::{reg::prelude::*, thr::prelude::*};
+use drone_stm32_map::periph::{
+    dma::{
+        periph_dma2,
+        periph_dma2_ch2,
+        periph_dma2_ch3,
+    },
+    gpio::{
+        periph_gpio_a_head,
+        periph_gpio_a5,
+        periph_gpio_a6,
+        periph_gpio_a7,
+    },
+    spi::{periph_spi1},
+};
+use drone_stm32f4_hal::spi::{SpiDrv, config::*};
 
 /// The root task handler.
 #[inline(never)]
@@ -12,6 +27,14 @@ pub fn handler(reg: Regs, thr_init: ThrsInit) {
 
     println!("Hello, world!");
 
+
+    let setup = SpiSetup::default(periph_spi1!(reg), thr.spi_1).at(Prsc::Prsc16);
+    let mut spi_drv = SpiDrv::init(setup);
+    let mut spi_master = spi_drv.master();
+
+    let tx_buf = [1,2,3,4].as_ref();
+    spi_master.send(tx_buf).root_wait();
+
     // Enter a sleep state on ISR exit.
     reg.scb_scr.sleeponexit.set_bit();
 }

examples/spi/src/thr.rs

@@ -26,5 +26,12 @@ thr! {
             /// All classes of faults.
             pub hard_fault;
         };
+        interrupts => {
+            // Vector table for stm32f429 is in PM0090 table 62 page 375.
+            5: pub rcc;
+            35: pub spi1;
+            58: pub dma2_ch2; // SPI1_RX: DMA2, stream 2 (channel 3).
+            59: pub dma2_ch3; // SPI1_TX: DMA2, stream 3 (channel 3).
+        }
     };
 }

examples/uart/uart.code-workspace

@@ -1,10 +1,10 @@
 {
 	"folders": [
 		{
-			"path": "../.."
+			"path": "."
 		},
 		{
-			"path": "."
+			"path": "../.."
 		},
 		{
 			"path": "../../../drone-stm32-map"

src/lib.rs

@@ -11,5 +11,8 @@ pub extern crate drone_stm32f4_gpio_drv as gpio;
 #[cfg(feature = "rcc")]
 pub extern crate drone_stm32f4_rcc_drv as rcc;
 
+#[cfg(feature = "spi")]
+pub extern crate drone_stm32f4_spi_drv as spi;
+
 #[cfg(feature = "uart")]
 pub extern crate drone_stm32f4_uart_drv as uart;

src/spi/drv.rs

@@ -1,6 +1,163 @@
+use crate::{
+    master::SpiMasterDrv,
+};
+use drone_cortexm::{fib, reg::prelude::*, thr::prelude::*};
+use drone_stm32_map::periph::{
+    dma::ch::{DmaChMap, DmaChPeriph},
+    spi::{traits::*, SpiMap, SpiPeriph},
+};
+
 pub mod config {
+    use super::*;
+
+    pub struct SpiSetup<Spi: SpiMap, SpiInt: IntToken> {
+        /// Spi peripheral.
+        pub spi: SpiPeriph<Spi>,
+        /// Spi global interrupt.
+        pub spi_int: SpiInt,
+        /// The baud rate clock prescaler.
+        /// baud_rate = f_pclk / baud_rate_prsc.
+        pub baud_rate_prsc: Prsc,
+        /// The clock polarity.
+        pub clk_pol: ClkPol,
+        /// The bit transmission order.
+        pub first_bit: FirstBit,
+    }
+
+    impl<Spi: SpiMap, SpiInt: IntToken> SpiSetup<Spi, SpiInt> {
+        /// Create a new spi setup with sensible defaults.
+        pub fn default(spi: SpiPeriph<Spi>, spi_int: SpiInt) -> SpiSetup<Spi, SpiInt> {
+            SpiSetup {
+                spi,
+                spi_int,
+                baud_rate_prsc: Prsc::Prsc2,
+                clk_pol: ClkPol::Low,
+                first_bit: FirstBit::Msb,
+            }
+        }
+
+        pub fn at(
+            mut self,
+            prsc: Prsc,
+        ) -> Self {
+            self.baud_rate_prsc = prsc;
+            self
+        }
+    }
+
+    pub enum Prsc {
+        Prsc2,
+        Prsc4,
+        Prsc8,
+        Prsc16,
+        Prsc32,
+        Prsc64,
+        Prsc128,
+        Prsc256,
+    }
+
+    pub enum ClkPol {
+        Low,
+        High
+    }
+
+    pub enum FirstBit {
+        Msb,
+        Lsb
+    }
+}
+
+pub struct SpiDrv<Spi: SpiMap, SpiInt: IntToken> {
+    spi: SpiPeriph<Spi>,
+    spi_int: SpiInt,
 }
 
-pub struct SpiDrv {
+impl<Spi: SpiMap, SpiInt: IntToken> SpiDrv<Spi, SpiInt> {
+    #[must_use]
+    pub fn init(setup: config::SpiSetup<Spi, SpiInt>) -> SpiDrv<Spi, SpiInt> {
+        let config::SpiSetup {
+            spi,
+            spi_int,
+            ..
+        } = setup;
+        let mut drv = SpiDrv {
+            spi,
+            spi_int
+        };
+        drv.init_spi();
+        drv
+    }
+
+    pub fn master(&mut self) -> SpiMasterDrv {
+        SpiMasterDrv {
+
+        }
+    }
+
+    fn init_spi(&mut self) {
+        // use self::config::*;
+
+        // // Enable uart clock.
+        // self.uart.rcc_busenr_uarten.set_bit();
+
+        // // Configure uart.
+        // self.uart.uart_cr1.store_reg(|r, v| {
+        //     // Do not enable uart before it is fully configured.
+
+        //     // Word length.
+        //     if data_bits == DataBits::Nine {
+        //         r.m().set(v);
+        //     }
+
+        //     // Parity.
+        //     if parity != Parity::None {
+        //         // Enable parity.
+        //         r.pce().set(v);
+        //         if parity == Parity::Odd {
+        //             // Parity selection: odd.
+        //             r.ps().set(v);
+        //         }
+        //     }
+
+        //     // Oversampling.
+        //     if oversampling == Oversampling::By8 {
+        //         r.over8().set(v);
+        //     }
+        // });
+        // self.uart.uart_cr2.store_reg(|r, v| {
+        //     // Stop bits.
+        //     r.stop().write(
+        //         v,
+        //         match stop_bits {
+        //             StopBits::One => 0,
+        //             StopBits::Half => 1,
+        //             StopBits::Two => 2,
+        //             StopBits::OneHalf => 3,
+        //         },
+        //     );
+        // });
+        // self.uart.uart_brr.store_reg(|r, v| {
+        //     // Baud rate.
+        //     let (div_man, div_frac) = clk.compute_brr(oversampling, baud_rate);
+        //     r.div_mantissa().write(v, div_man);
+        //     r.div_fraction().write(v, div_frac);
+        // });
+
+        // self.uart.uart_cr1.modify_reg(|r, v| {
+        //     // Enable parity error interrupt
+        //     r.peie().set(v);
+        //     // Enable ORE or RXNE interrupt
+        //     r.rxneie().set(v);
+        //     // Enable uart after being fully configured.
+        //     r.ue().set(v);
+        // });
 
+        // // Attach uart error handler
+        // let sr = self.uart.uart_sr;
+        // self.uart_int.add_fn(move || {
+        //     let val = sr.load_val();
+        //     handle_uart_err::<Uart>(&val, sr);
+        //     fib::Yielded::<(), !>(())
+        // });
+    }
 }

src/spi/master.rs

@@ -0,0 +1,19 @@
+pub struct SpiMasterDrv {
+
+}
+
+impl SpiMasterDrv {
+    pub async fn send(&mut self, tx_buf: &[u8]) -> usize {
+        tx_buf.len()
+    }
+
+    pub async fn xfer(&mut self, tx_buf: &[u8], rx_buf: &mut &[u8]) -> usize {
+        assert!(rx_buf.len() >= tx_buf.len());
+
+        tx_buf.len()
+    }
+
+    pub fn miso(&self) -> bool {
+        true
+    }
+}

src/uart/drv.rs

@@ -74,7 +74,7 @@ pub mod config {
 
     /// Uart clock configuration to be implemented by app adapter.
     pub trait UartClk {
-        /// The uart clock frequency.
+        /// The uart peripheral clock frequency.
         fn clock(&self) -> u32;
 
         /// Computes the uart divider for use by the baud rate register