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Add Zilx indexed integer load tests - #2250
Pengcheng Wang (wangpc-pp) wants to merge 5 commits into
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Heads-up: #2534 (merged) changed |
The CTP build hid failures, so broken test plan data and stale normative-rule names built without complaint. This makes the build fail on them and fixes their causes. **Makefile** - Each generator runs as its own recipe line. The test plan recipe chained them with `;`, so only the last exit status counted. - `norm-rules.json` is fetched once, as a target both generators depend on. It was written by one recipe and read only if present by another, which raced under `-j` and silently skipped the rule check. - A privileged suite with a YAML plan gets its table only from the YAML. SsstrictV's CSV table was being silently overwritten. - `ctp.adoc` includes `../common`, so the `build/common` and `build/docs-resources` links are no longer needed. - Docker mounts use `$(CURDIR)`, so `make -C docs/ctp` works. **Generators** - The fallback YAML parsers and the input-shape and path guessing are removed; no input used them. - Malformed entries, repeated rules, unknown UDB parameters and rule names missing from `norm-rules.json` are errors. The unread `mismatch_report.txt` is replaced by `build/unmapped-norm-rules.txt`. - A norm YAML for a suite not yet tagged in the ISA manual declares `untagged_upstream: <where the tags are pending>`. Its unknown names are warnings, and the build says when the key can be removed. **Data** - Rules the ISA manual merged are renamed (`vsha2chl-vv_*`, `Zvknha_Zvknhb_*`, `veccrypto_vl_vstart_*`, the Zvk dependency tags, `fflags_op_sz_acc`/`frm_op_sz_acc`). - Mappings for informative notes that riscv/riscv-isa-manual#3439, #3441 and #3442 untagged are removed, as are the six `Sdtrig_tdata1_type_*` names that riscv/riscv-isa-manual#3416 does not tag. Their coverpoints remain mapped by other rules. - SdtrigSm (riscv/riscv-isa-manual#3416) and Zibi are marked `untagged_upstream`. **Test plans** - In 43 suites that no open PR changes, `rules:` lists now hold only rule names: `norm:` wrappers are stripped, copied spec sentences and renamed rules use their current tags, and prose, questions and code move to notes. Plan rows use the coverpoint names the coverage files declare. - A row that names a family of crosses (`cp_x` for `cp_x_*`) now gets the rules mapped to those crosses. - The plan consistency checks remain warnings (about 550 are left, mostly in suites that riscv#2818, riscv#2810 and the suite-fold PRs change). In the cleaned suites, the ones left are planned coverpoints without covergroups (SvH, Smstateen, Ssstateen, ExceptionsHV) and Smmpm/SmnpmS/SmnpmU, whose plans omit the rows they share with Ssnpm. riscv#2790, riscv#2791 and riscv#2792 add `fflags_frm_op_sz_acc` to `U.yaml`, which now fails the build; it should be `[fflags_op_sz_acc, frm_op_sz_acc]`. riscv#2250 (Zilx) and riscv#2169 (Zvzip) will need `untagged_upstream`. 🤖 Generated with [Claude Code](https://claude.com/claude-code) --------- Signed-off-by: David Harris <David_Harris@hmc.edu> Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
Add CSV-driven RV32 and RV64 tests for all 19 Zilx instructions, including unscaled, scaled, and unsigned-word-index addressing modes. Use raw .insn encodings so the tests remain buildable before GCC gains Zilx mnemonic support. Add functional coverage, decode and disassembly support, normative-rule mappings, CTP integration, and regenerated checked-in test artifacts. Specification: https://github.com/riscv/riscv-zilx Assisted-by: TRAE CLI (GPT-5) Signed-off-by: Pengcheng Wang <wangpengcheng.pp@bytedance.com>
Use the current covergroup template placeholder for indexed loads. Regenerate the affected RV64 tests and coverage for new edge values. Existing Zilx rule keys already match their ISA-manual norm tags. Update the file description to state that format. Assisted-by: TRAE CLI (GPT-5) Signed-off-by: Pengcheng Wang <wangpengcheng.pp@bytedance.com>
Regenerate the Zilx sampler with the current covergroup generator. Assisted-by: TRAE CLI (GPT-5) Signed-off-by: Pengcheng Wang <wangpengcheng.pp@bytedance.com>
Gate Zilx tests through the common experimental-extension path. Run them in the dedicated Spike configuration. Use the UDB-supported 0.1.0 configuration version. Keep raw instruction encodings for compiler portability. Assisted-by: TRAE CLI (GPT-5) Signed-off-by: Pengcheng Wang <wangpengcheng.pp@bytedance.com>
Record the current specification version. Rename the unscaled-byte reserved-encoding rule to match its normative tag. Assisted-by: TRAE CLI (GPT-5) Signed-off-by: Pengcheng Wang <wangpengcheng.pp@bytedance.com>
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Gentle ping! Zilx is now in Freeze process and I hope we can help to review this ACT PR to push the ratification forward! |
Add CSV-driven RV32 and RV64 tests for all 19 Zilx instructions, including unscaled, scaled, and unsigned-word-index addressing modes. Use raw .insn encodings so the tests remain buildable before GCC gains Zilx mnemonic support.
Add functional coverage, decode and disassembly support, normative-rule mappings, CTP integration, and regenerated checked-in test artifacts.
Specification: https://github.com/riscv/riscv-zilx/blob/main/src/unpriv/zilx.adoc