Adding support for the Zalasr (Load-acquire and store-release) extension

CHANGELOG.md

@@ -6,6 +6,9 @@ Please note the header `WIP-DEV` is to always remain indicating the changes done
 Only when a release to the main branch is done, the contents of the WIP-DEV are put under a
 versioned header while the `WIP-DEV` is left empty
 
+## [WIP-DEV] - 2024-05-08
+- Added support for Zalasr unratified extension
+
 ## [0.12.1] - 2024-02-27
 - Fix test.yml
 

riscv_ctg/data/template.yaml

@@ -12661,3 +12661,150 @@ ssrdp_u:
     #define ZICFISS_SETUP_DONE 1
     #endif
     TEST_SSRDP_OP(ssrdp, $rd, $swreg, $testreg, Umode)
+lb.aq:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I_Zalasr
+  formattype: 'rformat'
+  ea_align_data: '[0,1,2,3]'
+  template: |-
+
+    // $comment
+    // opcode:$inst op1:$rs1; dest:$rd; align:$ea_align
+    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,0,$offset,$inst,$ea_align)
+
+lh.aq:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I_Zalasr
+  formattype: 'rformat'
+  ea_align_data: '[0,1,2,3]'
+  template: |-
+
+    // $comment
+    // opcode:$inst op1:$rs1; dest:$rd; align:$ea_align
+    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,0,$offset,$inst,$ea_align)
+
+lw.aq:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I_Zalasr
+  formattype: 'rformat'
+  ea_align_data: '[0,1,2,3]'
+  template: |-
+
+    // $comment
+    // opcode:$inst op1:$rs1; dest:$rd; align:$ea_align
+    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,0,$offset,$inst,$ea_align)
+
+ld.aq:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rd_op_data: *all_regs
+  xlen: [64]
+  std_op:
+  isa: 
+    - I_Zalasr
+  formattype: 'rformat'
+  ea_align_data: '[0,1,2,3,4,5,6,7]'
+  template: |-
+
+    // $comment
+    // opcode:$inst op1:$rs1; dest:$rd; align:$ea_align
+    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,0,$offset,$inst,$ea_align)
+
+sb.rl:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I_Zalasr
+  formattype: 'rformat'
+  ea_align_data: '[0,1,2,3]'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; align:$ea_align
+    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,0,$offset,$inst,$ea_align)
+
+sh.rl:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I_Zalasr
+  formattype: 'rformat'
+  ea_align_data: '[0,1,2,3]'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; align:$ea_align
+    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,0,$offset,$inst,$ea_align)
+
+sw.rl:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I_Zalasr
+  formattype: 'rformat'
+  ea_align_data: '[0,1,2,3]'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; align:$ea_align
+    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,0,$offset,$inst,$ea_align)
+
+sd.rl:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  xlen: [64]
+  std_op:
+  isa: 
+    - I_Zalasr
+  formattype: 'rformat'
+  ea_align_data: '[0,1,2,3,4,5,6,7]'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; align:$ea_align
+    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,0,$offset,$inst,$ea_align)

sample_cgfs/rv32zalasr.cgf

@@ -0,0 +1,101 @@
+# cover group format file for Zalasr extension
+lb.aq:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    opcode: 
+      lb.aq 0
+    rs1: 
+      <<: *all_regs_mx0
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      'ea_align == 0'
+      'ea_align == 1'
+      'ea_align == 2'
+      'ea_align == 3'
+
+lh.aq:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    opcode: 
+      lh.aq 0
+    rs1: 
+      <<: *all_regs_mx0
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      'ea_align == 0'
+      'ea_align == 2'
+
+lw.aq:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    opcode: 
+      lw.aq 0
+    rs1: 
+      <<: *all_regs_mx0
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      'ea_align == 0'
+
+sb.rl:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    opcode: 
+      sb.rl 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    op_comb: 
+        'rs1 != rs2': 0
+    val_comb:
+        'ea_align == 0': 0
+        'ea_align == 1': 0
+        'ea_align == 2': 0
+        'ea_align == 3': 0
+        <<: [  *base_rs2val_sgn]
+        abstract_comb:
+          <<: [*rs2val_walking]
+
+sh.rl:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    opcode: 
+      sh.rl 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    op_comb: 
+        'rs1 != rs2': 0
+    val_comb:
+        'ea_align == 0': 0
+        'ea_align == 2': 0
+        <<: [  *base_rs2val_sgn]
+        abstract_comb:
+          <<: [*rs2val_walking]
+
+sw.rl:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    opcode: 
+      sw.rl 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    op_comb: 
+        'rs1 != rs2': 0
+    val_comb:
+        'ea_align == 0': 0
+        <<: [  *base_rs2val_sgn]
+        abstract_comb:
+          <<: [*rs2val_walking]

sample_cgfs/rv64zalasr.cgf

@@ -0,0 +1,132 @@
+# cover group format file for Zalasr extension
+lb.aq:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    opcode: 
+      lb.aq 0
+    rs1: 
+      <<: *all_regs_mx0
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      'ea_align == 0'
+      'ea_align == 1'
+      'ea_align == 2'
+      'ea_align == 3'
+
+lh.aq:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    opcode: 
+      lh.aq 0
+    rs1: 
+      <<: *all_regs_mx0
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      'ea_align == 0'
+      'ea_align == 2'
+
+lw.aq:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    opcode: 
+      lw.aq 0
+    rs1: 
+      <<: *all_regs_mx0
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      'ea_align == 0'
+
+ld.aq:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    opcode: 
+      ld.aq 0
+    rs1: 
+      <<: *all_regs_mx0
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      'ea_align == 0'
+
+sb.rl:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    opcode: 
+      sb.rl 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    op_comb: 
+        'rs1 != rs2': 0
+    val_comb:
+        'ea_align == 0': 0
+        'ea_align == 1': 0
+        'ea_align == 2': 0
+        'ea_align == 3': 0
+        <<: [  *base_rs2val_sgn]
+        abstract_comb:
+          <<: [*rs2val_walking]
+
+sh.rl:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    opcode: 
+      sh.rl 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    op_comb: 
+        'rs1 != rs2': 0
+    val_comb:
+        'ea_align == 0': 0
+        'ea_align == 2': 0
+        <<: [  *base_rs2val_sgn]
+        abstract_comb:
+          <<: [*rs2val_walking]
+
+sw.rl:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    opcode: 
+      sw.rl 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    op_comb: 
+        'rs1 != rs2': 0
+    val_comb:
+        'ea_align == 0': 0
+        <<: [  *base_rs2val_sgn]
+        abstract_comb:
+          <<: [*rs2val_walking]
+
+sd.rl:
+    config: 
+      - check ISA:=regex(.*Zalasr.*)
+    opcode: 
+      sd.rl 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    op_comb: 
+        'rs1 != rs2': 0
+    val_comb:
+        'ea_align == 0': 0
+        <<: [  *base_rs2val_sgn]
+        abstract_comb:
+          <<: [*rs2val_walking]