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Yet another classic five stage pipelined MIPS processor

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NaiveCPU

This is a course project for Computer Organization in Tsinghua University.

We have implemented a classic five stage pipelined CPU on a Spartan-3E based board. The instruction set architecture we used is derived from MIPS16e.

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MIT License

"Copy and Paste" is fine, because we know it's not easy to build a CPU from scratch.

And we did benefit a lot from copying code written by others in this project.

Just make sure you understand what you are doing.

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Yet another classic five stage pipelined MIPS processor

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