Skip to content

For sufficiently large cyw43 PIO SPI transfers, sleep via async_context before entering busy wait. #2344

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 3 commits into
base: develop
Choose a base branch
from
Open

For sufficiently large cyw43 PIO SPI transfers, sleep via async_context before entering busy wait. #2344

Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
fe20f37
- For sufficiently large cyw43 PIO SPI transfers, sleep via async_con…
esky-software Mar 10, 2025
a71a8d3
Add PICO_CONFIG description for CYW43_PIO_SLEEP_MIN_US
esky-software Apr 5, 2025
833d3de
Update cyw43_bus_pio_spi.c
esky-software May 8, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
22 changes: 22 additions & 0 deletions src/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,18 @@ void cyw43_set_pio_clkdiv_int_frac8(uint32_t clock_div_int, uint8_t clock_div_fr
}
#endif

// PICO_CONFIG: CYW43_PIO_SLEEP_MIN_US, For PIO SPI transfers longer than this (in microseconds), sleep via async_context before entering busy wait, type=int, default=disabled, group=pico_cyw43_driver
#if CYW43_PIO_SLEEP_MIN_US
static uint32_t bit_rate_khz;
static void sleep_if_long_transfer(uint32_t xfr_length)
{
// Estimate transfer delay & sleep for about that long if it's long enough
unsigned xfr_us = (xfr_length * 8 * 1000) / bit_rate_khz;
if (xfr_us > CYW43_PIO_SLEEP_MIN_US)
cyw43_delay_us(xfr_us);
}
#endif

#define PADS_DRIVE_STRENGTH PADS_BANK0_GPIO0_DRIVE_VALUE_12MA

#if !CYW43_USE_SPI
Expand Down Expand Up @@ -122,6 +134,10 @@ int cyw43_spi_init(cyw43_int_t *self) {
}
pio_sm_config config = SPI_PROGRAM_GET_DEFAULT_CONFIG_FUNC(bus_data->pio_offset);

#if CYW43_PIO_SLEEP_MIN_US
// 2 PIO cycles per bit, PIO clock scaled
bit_rate_khz = clock_get_hz(clk_sys) / (cyw43_pio_clock_div_int * 2 * 1000);
#endif
sm_config_set_clkdiv_int_frac8(&config, cyw43_pio_clock_div_int, cyw43_pio_clock_div_frac8);
hw_write_masked(&pads_bank0_hw->io[CYW43_PIN_WL_CLOCK],
(uint)PADS_DRIVE_STRENGTH << PADS_BANK0_GPIO0_DRIVE_LSB,
Expand Down Expand Up @@ -277,6 +293,9 @@ int cyw43_spi_transfer(cyw43_int_t *self, const uint8_t *tx, size_t tx_length, u
pio_sm_set_enabled(bus_data->pio, bus_data->pio_sm, true);
__compiler_memory_barrier();

#if CYW43_PIO_SLEEP_MIN_US
sleep_if_long_transfer(MAX(tx_length, rx_length));
#endif
dma_channel_wait_for_finish_blocking(bus_data->dma_out);
dma_channel_wait_for_finish_blocking(bus_data->dma_in);

Expand Down Expand Up @@ -309,6 +328,9 @@ int cyw43_spi_transfer(cyw43_int_t *self, const uint8_t *tx, size_t tx_length, u
dma_channel_configure(bus_data->dma_out, &out_config, &bus_data->pio->txf[bus_data->pio_sm], tx, tx_length / 4, true);

pio_sm_set_enabled(bus_data->pio, bus_data->pio_sm, true);
#if CYW43_PIO_SLEEP_MIN_US
sleep_if_long_transfer(tx_length);
#endif
dma_channel_wait_for_finish_blocking(bus_data->dma_out);

uint32_t fdebug_tx_stall = 1u << (PIO_FDEBUG_TXSTALL_LSB + bus_data->pio_sm);
Expand Down