fixing verilog placeholder pass #277
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@ptpan can you take a look? |
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Hmm.. As I recall we had support for this before. Not sure why it is missing? |
Improve index handling in Bits and Signal classes
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I also saw that in the Doc, which surprised me, this is not working. When I do a repo-wide search, the |
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The placeholder pass wrapper does not add a clock and reset signal, even when the metadata is set, which causes a missing pin warning from Verilator.
Furthermore, the name of the clock and reset might vary between designs; two new parameters are added so that the user can define the name of the clock signal and the reset signal.