Introduction to SystemVerilog examples

This repository contains the source files of the 'Introduction to SystemVerilog' book examples.

'Introduction to SystemVerilog' and examples by Ashok B. Mehta, Springer ISBN 978-3-030-71321-8 and ISBN 978-3-030-71319-5

Simulation

Use the root Makefile which supports the below simulators.

Run as follows to learn about the supported targets:

make help

To simulate, run the generated binaries manually from their respective directory.

To remove the generated files, run:

make clean

Questa

The author reports that all examples simulate fine with the (commercial) Questa.

Verilator

Ensure your directory path does not contain spaces for binary creation to work.

Currently with v5.046, 189 out of 243 compile fine, the failing ones likely containing unsupported SystemVerilog syntax/features.

Icarus Verilog (iverilog)

Currently with v13, 120 out of 243 files compile fine, the failing ones likely containing unsupported SystemVerilog syntax/features.

Performance comparison

Icarus Verilog is clearly faster for compilation (elaboration) because it acts as an interpreter-based simulator, whereas Verilator is a compiler-based simulator that performs a computationally heavy translation of HDL into optimized C++ code. While Icarus is faster to start, Verilator should be vastly faster in simulation execution speed for large designs which is not the case for these examples.