Designed an RTL model for a Timer_IP using Verilog HDL on a Linux server, implementing a 64-bit counter with configurable divider, interrupt generation, and APB interface. Developed a comprehensive testbench in Verilog to verify functionality across multiple modes, including timer enable, divider enable, and divider values (0 to 8). Implemented test cases to validate counter operation, interrupt triggering, and register read/write operations via APB protocol, ensuring accurate 64-bit counting and comparison. Conducted simulations in ModelSim, analyzed waveforms to verify timing and functional correctness, and debugged issues. Documented test plan, verification results, and module specifications for integration into embedded systems