feat(kernels): pool-write prep for Gemma 4 serving at both head dims - #881
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Signed-off-by: Feathbow <feathbow@gmail.com>
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Description
Fixes #880
The write-side prep entries the Gemma 4 serving path needs, at both head dims:
v_proj):qkv_norm_rope_paged_prefill_hd256_plain_into, the serving form of feat(kernels): plain-w QK-norm and RoPE prep at head_dim 256 #853's oracle-form prep — Q normed + rotated into a contiguousq_out, K normed + rotated and V weightless-normed (never rotated) scattered straight into the layer's K/V pool blocks in one kernel, no intermediate scatter.inv_rmsdenominator, in the same pass. No separate v_proj input and no D2D fork copy; the fork semantics are the ones feat(gemma4): global decoder layer and its HF golden oracle probes #877 pinned against the reference.Both wrappers derive their pool geometry through one checked helper: the layout's fields are public, so the block and stride arithmetic is re-derived with overflow-checked multiplies, asserted against the layout, and narrowed through checked conversions before anything reaches the unsafe launch; each wrapper additionally checks that its q/kv widths, tensor extents and rope-table length fit the 32-bit arithmetic the kernel indexes with — a contradictory or wrapping layout fails as an
Err, never as a release-mode wrap or a divide-by-zero. On top of that sit the layer bound, whole-page pools, page coverage of[start_pos, start_pos + seq_len)(checked addition), position range against the rope tables, table lengths and vec-backed weights; the kernels__trap()on out-of-range positions or page ids as the second layer of that defence. Slot positions derive fromstart_pos + token— absolute and cache-relative coordinates coincide below the sliding window, which is the entries' documented contract; window-crossing callers need a separate slot mapping first.Test Env
Single GPU (sm_89, x86_64), CUDA 12.9,
PEGAINFER_REQUIRE_GPU=1.Verification
Type of Change