Skip to content

[GR-67700] Mark k0 register as not allocatable #11705

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Jul 21, 2025
Merged

[GR-67700] Mark k0 register as not allocatable #11705

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
14 changes: 8 additions & 6 deletions ...vm.core.graal.amd64/src/com/oracle/svm/core/graal/amd64/SubstrateAMD64RegisterConfig.java
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,7 @@
package com.oracle.svm.core.graal.amd64;

import static com.oracle.svm.core.util.VMError.unsupportedFeature;
import static jdk.vm.ci.amd64.AMD64.k0;
import static jdk.vm.ci.amd64.AMD64.k1;
import static jdk.vm.ci.amd64.AMD64.k2;
import static jdk.vm.ci.amd64.AMD64.k3;
Expand Down Expand Up @@ -129,14 +130,14 @@ public SubstrateAMD64RegisterConfig(ConfigKind config, MetaAccessProvider metaAc
boolean haveAVX512 = ((AMD64) target.arch).getFeatures().contains(AMD64.CPUFeature.AVX512F);
ArrayList<Register> regs;
if (haveAVX512) {
/*
* GR-40969: We would like to use valueRegistersAVX512. However, we emit a mix of VEX
* and EVEX encoded instructions, and the VEX variants cannot address the extended
* AVX-512 registers (XMM16-31). For now, limit ourselves to XMM0-15.
*/
regs = new ArrayList<>();
regs.addAll(valueRegistersAVX512);
regs.addAll(MASK_REGISTERS);
/*
* valueRegistersAVX512 contains all mask registers, including k0. k0 is not a general
* allocatable register, most instructions that read it interpret it as "no opmask"
* rather than as a real opmask register.
*/
regs.remove(k0);
} else {
regs = new ArrayList<>();
regs.addAll(valueRegistersSSE);
Expand All @@ -146,6 +147,7 @@ public SubstrateAMD64RegisterConfig(ConfigKind config, MetaAccessProvider metaAc
regs.addAll(MASK_REGISTERS);
}
}
VMError.guarantee(!regs.contains(k0), "We must never treat k0 as a general allocatable register.");

if (Platform.includedIn(InternalPlatform.WINDOWS_BASE.class)) {
// This is the Windows 64-bit ABI for parameters.
Expand Down