[Intel-SIG] DMR APX support - kernel-host part#117
Open
quanxianwang wants to merge 32 commits into6.6-velinuxfrom
Open
[Intel-SIG] DMR APX support - kernel-host part#117quanxianwang wants to merge 32 commits into6.6-velinuxfrom
quanxianwang wants to merge 32 commits into6.6-velinuxfrom
Conversation
quanxianwang
force-pushed
the
DMR-APX
branch
from
3900869 to
d73c98d
Compare
commit 99c8431 upstream. Skip instead of failing when prerequisite conditions aren't fulfilled, such as invalid xstate values etc. Make the tests show as 'SKIP' when run: make -C tools/testing/selftests/ TARGETS=x86 run_tests ... # timeout set to 45 # selftests: x86: amx_64 # # xstate cpuid: invalid tile data size/offset: 0/0 ok 42 selftests: x86: amx_64 # SKIP # timeout set to 45 # selftests: x86: lam_64 # # Unsupported LAM feature! ok 43 selftests: x86: lam_64 # SKIP ... In the AMX test, Move away from check_cpuid_xsave() and start using arch_prctl() to find out if AMX support is present or not. In the kernels where AMX isn't present, arch_prctl() returns -EINVAL, hence it is backward compatible. Intel-SIG: commit 99c8431 x86/selftests: Skip the tests if prerequisites aren't fulfilled. DMR ISA APX enabling - HOST Signed-off-by: Muhammad Usama Anjum <usama.anjum@collabora.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Chang S. Bae <chang.seok.bae@intel.com> Reviewed-by: Binbin Wu <binbin.wu@linux.intel.com> Acked-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Link: https://lore.kernel.org/r/20240327111720.3509180-1-usama.anjum@collabora.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit 7d17b29 upstream. When building with clang, via: make LLVM=1 -C tools/testing/selftests ...quite a few functions are variables are generating "unused" warnings. Fix the warnings by deleting the unused items. One item, the "nerrs" variable in vsdo_restorer.c's main(), is unused but probably wants to be returned from main(), as a non-zero result. That result is also unused right now, so another option would be to delete it entirely, but this way, main() also gets fixed. It was missing a return value. Intel-SIG: commit 7d17b29 selftests/x86: remove (or use) unused variables and functions. DMR ISA APX enabling - HOST Acked-by: Muhammad Usama Anjum <usama.anjum@collabora.com> Signed-off-by: John Hubbard <jhubbard@nvidia.com> Signed-off-by: Shuah Khan <skhan@linuxfoundation.org> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit 825658b upstream. When building with clang, via: make LLVM=1 -C tools/testing/selftests ...the following build failure occurs in selftests/x86: clang: error: cannot specify -o when generating multiple output files This happens because, although gcc doesn't complain if you invoke it like this: gcc file1.c header2.h ...clang won't accept that form--it rejects the .h file(s). Also, the above approach is inaccurate anyway, because file.c includes header2.h in this case, and the inclusion of header2.h on the invocation is an artifact of the Makefile's desire to maintain dependencies. In Makefiles of this type, a better way to do it is to use Makefile dependencies to trigger the appropriate incremental rebuilds, and separately use file lists (see EXTRA_FILES in this commit) to track what to pass to the compiler. This commit splits those concepts up, by setting up both EXTRA_FILES and the Makefile dependencies with a single call to the new Makefile function extra-files. That fixes the build failure, while still providing the correct dependencies in all cases. Intel-SIG: commit 825658b selftests/x86: fix Makefile dependencies to work with clang. DMR ISA APX enabling - HOST Acked-by: Muhammad Usama Anjum <usama.anjum@collabora.com> Signed-off-by: John Hubbard <jhubbard@nvidia.com> Signed-off-by: Shuah Khan <skhan@linuxfoundation.org> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit 84ee6e8 upstream. In the case where a user thread sets up an alternate signal stack protected by the default PKEY (i.e. PKEY 0), while the thread's stack is protected by a non-zero PKEY, both these PKEYS have to be enabled in the PKRU register for the signal to be delivered to the application correctly. However, the PKRU value restored after handling the signal must not enable this extra PKEY (i.e. PKEY 0) - i.e., the PKRU value in the sigframe has to be overwritten with the user-defined value. Add helper functions that will update PKRU value in the sigframe after XSAVE. Note that sig_prepare_pkru() makes no assumption about which PKEY could be used to protect the altstack (i.e. it may not be part of init_pkru), and so enables all PKEYS. No functional change. Intel-SIG: commit 84ee6e8 x86/pkeys: Add helper functions to update PKRU on the sigframe. DMR ISA APX enabling - HOST Signed-off-by: Aruna Ramakrishna <aruna.ramakrishna@oracle.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20240802061318.2140081-3-aruna.ramakrishna@oracle.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit 70044df upstream. If the alternate signal stack is protected by a different PKEY than the current execution stack, copying XSAVE data to the sigaltstack will fail if its PKEY is not enabled in the PKRU register. It's unknown which pkey was used by the application for the altstack, so enable all PKEYS before XSAVE. But this updated PKRU value is also pushed onto the sigframe, which means the register value restored from sigcontext will be different from the user-defined one, which is incorrect. Fix that by overwriting the PKRU value on the sigframe with the original, user-defined PKRU. Intel-SIG: commit 70044df x86/pkeys: Update PKRU to enable all pkeys before XSAVE. DMR ISA APX enabling - HOST Signed-off-by: Aruna Ramakrishna <aruna.ramakrishna@oracle.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20240802061318.2140081-4-aruna.ramakrishna@oracle.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit 6a1853bdf17874392476b552398df261f75503e0 upstream. update_pkru_in_sigframe() will shortly need some information which is only available inside xsave_to_user_sigframe(). Move update_pkru_in_sigframe() inside the other function to make it easier to provide it that information. No functional changes. Intel-SIG: commit 6a1853bdf178 x86/pkeys: Change caller of update_pkru_in_sigframe(). DMR ISA APX enabling - HOST Signed-off-by: Aruna Ramakrishna <aruna.ramakrishna@oracle.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Link: https://lore.kernel.org/all/20241119174520.3987538-2-aruna.ramakrishna%40oracle.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit ae6012d72fa60c9ff92de5bac7a8021a47458e5b upstream. When XSTATE_BV[i] is 0, and XRSTOR attempts to restore state component 'i' it ignores any value in the XSAVE buffer and instead restores the state component's init value. This means that if XSAVE writes XSTATE_BV[PKRU]=0 then XRSTOR will ignore the value that update_pkru_in_sigframe() writes to the XSAVE buffer. XSTATE_BV[PKRU] only gets written as 0 if PKRU is in its init state. On Intel CPUs, basically never happens because the kernel usually overwrites the init value (aside: this is why we didn't notice this bug until now). But on AMD, the init tracker is more aggressive and will track PKRU as being in its init state upon any wrpkru(0x0). Unfortunately, sig_prepare_pkru() does just that: wrpkru(0x0). This writes XSTATE_BV[PKRU]=0 which makes XRSTOR ignore the PKRU value in the sigframe. To fix this, always overwrite the sigframe XSTATE_BV with a value that has XSTATE_BV[PKRU]==1. This ensures that XRSTOR will not ignore what update_pkru_in_sigframe() wrote. The problematic sequence of events is something like this: Userspace does: * wrpkru(0xffff0000) (or whatever) * Hardware sets: XINUSE[PKRU]=1 Signal happens, kernel is entered: * sig_prepare_pkru() => wrpkru(0x00000000) * Hardware sets: XINUSE[PKRU]=0 (aggressive AMD init tracker) * XSAVE writes most of XSAVE buffer, including XSTATE_BV[PKRU]=XINUSE[PKRU]=0 * update_pkru_in_sigframe() overwrites PKRU in XSAVE buffer ... signal handling * XRSTOR sees XSTATE_BV[PKRU]==0, ignores just-written value from update_pkru_in_sigframe() Fixes: 70044df ("x86/pkeys: Update PKRU to enable all pkeys before XSAVE") Intel-SIG: commit ae6012d72fa6 x86/pkeys: Ensure updated PKRU value is XRSTOR'd. DMR ISA APX enabling - HOST Suggested-by: Rudi Horn <rudi.horn@oracle.com> Signed-off-by: Aruna Ramakrishna <aruna.ramakrishna@oracle.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Acked-by: Dave Hansen <dave.hansen@linux.intel.com> Link: https://lore.kernel.org/all/20241119174520.3987538-3-aruna.ramakrishna%40oracle.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit dbd6b649e7d5b66c7fa95a65d67b59cf5b45f0ac upstream. The x86 selftests frequently register and clean up signal handlers, but the sethandler() and clearhandler() functions have been redundantly copied across multiple .c files. Move these functions to helpers.h to enable reuse across tests, eliminating around 250 lines of duplicate code. Converge the error handling by using ksft_exit_fail_msg(), which is functionally equivalent with err() within the selftest framework. This change is a prerequisite for the upcoming xstate selftest, which requires signal handling for registering and cleaning up handlers. Intel-SIG: commit dbd6b649e7d5 selftests/x86: Consolidate redundant signal helper functions. DMR ISA APX enabling - HOST Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20250226010731.2456-2-chang.seok.bae@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit 0f6d91a327db4a36d6febb74d833cdc668c8661b upstream. The AMX test introduced several XSAVE-related helper functions, but so far, it has been the only user of them. These helpers can be generalized for broader test of multiple xstate features. Move most XSAVE-related code into xsave.h, making it shareable. The restructuring includes: * Establishing low-level XSAVE helpers for saving and restoring register states, as well as handling XSAVE buffers. * Generalizing state data manipuldations: set_rand_data() * Introducing a generic feature query helper: get_xstate_info() While doing so, remove unused defines in amx.c. Intel-SIG: commit 0f6d91a327db selftests/x86/xstate: Refactor XSAVE helpers for general use. DMR ISA APX enabling - HOST Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20250226010731.2456-3-chang.seok.bae@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit 3fcb4d61465613aee76ebd5d86b488778657dda7 upstream. After moving essential helpers from amx.c, the code remains neutral regarding which xstate components it handles. However, explicitly listing known components helps users identify which features are ready for testing. Enumerate xstate components to facilitate identification. Extend struct xstate_info to include a name field, providing a human-readable identifier. Intel-SIG: commit 3fcb4d614656 selftests/x86/xstate: Enumerate and name xstate components. DMR ISA APX enabling - HOST Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20250226010731.2456-4-chang.seok.bae@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit 40f6852ef2bffcd6fb3634cf71e6fbc2d1d6b768 upstream. The existing context switching and ptrace tests in amx.c are not specific to dynamic states, making them reusable for general xstate testing. As a first step, move the context switching test to xstate.c. Refactor the test code to allow specifying which xstate component being tested. To decouple the test from dynamic states, remove the permission request code. In fact, The permission request inside the test wrapper was redundant. Additionally, replace fatal_error() with ksft_exit_fail_msg() for consistency in error handling. Expected output: $ amx_64 ... [RUN] AMX Tile data: check context switches, 10 iterations, 5 threads. [OK] No incorrect case was found. Intel-SIG: commit 40f6852ef2bf selftests/x86/xstate: Refactor context switching test. DMR ISA APX enabling - HOST Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20250226010731.2456-5-chang.seok.bae@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit 7cb2fbe41949caa35ef1805323b8fc011fac2537 upstream. Following the refactoring of the context switching test, the ptrace test is another component reusable for other xstate features. As part of this restructuring, add a missing check to validate the user_xstateregs->xstate_fx_sw field in the ABI. Also, replace err() and fatal_error() with ksft_exit_fail_msg() for consistency in error handling. Expected output: $ amx_64 ... [RUN] AMX Tile data: inject xstate via ptrace(). [OK] 'xfeatures' in SW reserved area was correctly written [OK] xstate was correctly updated. Intel-SIG: commit 7cb2fbe41949 selftests/x86/xstate: Refactor ptrace ABI test. DMR ISA APX enabling - HOST Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20250226010731.2456-6-chang.seok.bae@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit e075d9fa16b3681b8a375cb47f4b5a1901e93530 upstream. With the refactored test cases, another xstate exposure to userspace is through signal delivery. While amx.c includes signal-related scenarios, its primary focus is on xstate permission management, which is largely specific to dynamic states. The remaining gap is testing xstate preservation and restoration across signal delivery. The kernel defines an ABI for presenting xstate in the signal frame, closely resembling the hardware XSAVE format, where xstate modification is also possible. Introduce a new test case to verify xstate preservation across signal delivery and return, that is ensuring ABI compatibility by: - Loading xstate before raising a signal. - Verifying correct exposure in the signal frame - Modifying xstate in the signal frame before returning. - Checking the state restoration upon signal return. Integrate this test into the AMX test suite as an initial usage site. Expected output: $ amx_64 ... [RUN] AMX Tile data: load xstate and raise SIGUSR1 [OK] 'magic1' is valid [OK] 'xfeatures' in SW reserved area is valid [OK] 'xfeatures' in XSAVE header is valid [OK] xstate delivery was successful [OK] 'magic2' is valid [RUN] AMX Tile data: load new xstate from sighandler and check it after sigreturn [OK] xstate was restored correctly Intel-SIG: commit e075d9fa16b3 selftests/x86/xstate: Introduce signal ABI test. DMR ISA APX enabling - HOST Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20250226010731.2456-7-chang.seok.bae@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit 10d8a204c5009fb8a6cb2790d17b5611b795c349 upstream. Currently, each of the three xstate tests runs as a separate invocation, requiring the xstate number to be passed and state information to be reconstructed repeatedly. This approach arose from their individual and isolated development, but now it makes sense to unify them. Introduce a wrapper function that first verifies feature availability from the kernel and constructs the necessary state information once. The wrapper then sequentially invokes all tests to ensure consistent execution. Update the AMX test to use this unified invocation. Intel-SIG: commit 10d8a204c500 selftests/x86/xstate: Consolidate test invocations into a single entry. DMR ISA APX enabling - HOST Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20250226010731.2456-8-chang.seok.bae@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit fa826c1f2cc92db44c207d323d2568e3f04c1257 upstream. The established xstate test code is designed to be generic, but certain xstates require special handling and cannot be tested without additional adjustments. Clarify which xstates are currently supported, and enforce testing only for them. Intel-SIG: commit fa826c1f2cc9 selftests/x86/xstate: Clarify supported xstates. DMR ISA APX enabling - HOST Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20250226010731.2456-9-chang.seok.bae@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit bfc98dbcb3c75c6e2eb1dcf389d02a8c2419c41c upstream. Add xstate testing specifically for those vector register states, validating kernel's context switching and ensuring ABI compliance. Use the established xstate testing framework. Alternatively, this invocation could be placed directly in xstate.c::main(). However, the current test file naming convention, which clearly specifies the tested area, seems reasonable. Adding avx.c considerably aligns with that convention. The test output should be like this for ZMM_Hi256 as an example: $ avx_64 ... [RUN] AVX-512 ZMM_Hi256: check context switches, 10 iterations, 5 threads. [OK] No incorrect case was found. [RUN] AVX-512 ZMM_Hi256: inject xstate via ptrace(). [OK] 'xfeatures' in SW reserved area was correctly written [OK] xstate was correctly updated. [RUN] AVX-512 ZMM_Hi256: load xstate and raise SIGUSR1 [OK] 'magic1' is valid [OK] 'xfeatures' in SW reserved area is valid [OK] 'xfeatures' in XSAVE header is valid [OK] xstate delivery was successful [OK] 'magic2' is valid [RUN] AVX-512 ZMM_Hi256: load new xstate from sighandler and check it after sigreturn [OK] xstate was restored correctly But systems without AVX-512 will look like: ... The kernel does not support feature number: 5 The kernel does not support feature number: 6 The kernel does not support feature number: 7 Intel-SIG: commit bfc98dbcb3c7 selftests/x86/avx: Add AVX tests. DMR ISA APX enabling - HOST Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20250226010731.2456-10-chang.seok.bae@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit 69a2fdf446049ae31be4a14a0cf16f2f18f09b6c upstream. print_xstate_features() currently invokes print_xstate_feature() multiple times on separate lines, which can be simplified in a loop. print_xstate_feature() already checks the feature's enabled status and is only called within print_xstate_features(). Inline print_xstate_feature() and iterate over features in a loop to streamline the enabling message. No functional changes. Intel-SIG: commit 69a2fdf44604 x86/fpu/xstate: Simplify print_xstate_features(). DMR ISA APX enabling - HOST Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com> Link: https://lore.kernel.org/r/20250227184502.10288-2-chang.seok.bae@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit 031b33ef1a6a1129a1a02a16b89608ded2eff9be upstream. Traditionally, new xstate components have been assigned sequentially, aligning feature numbers with their offsets in the XSAVE buffer. However, this ordering is not architecturally mandated in the non-compacted format, where a component's offset may not correspond to its feature number. The kernel caches CPUID-reported xstate component details, including size and offset in the non-compacted format. As part of this process, a sanity check is also conducted to ensure alignment between feature numbers and offsets. This check was likely intended as a general guideline rather than a strict requirement. Upcoming changes will support out-of-order offsets. Remove the check as becoming obsolete. Intel-SIG: commit 031b33ef1a6a x86/fpu/xstate: Remove xstate offset check. DMR ISA APX enabling - HOST Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Andy Lutomirski <luto@kernel.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Link: https://lore.kernel.org/r/20250320234301.8342-2-chang.seok.bae@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit 15d51a2f6f3f7057311d6e37d5190d58597a94a9 upstream. The kernel has largely assumed that higher xstate component numbers correspond to later offsets in the buffer. However, this assumption no longer holds for the non-compacted format, where a newer state component may have a lower offset. When iterating over xstate components in offset order, using the feature number as an index may be misleading. At the same time, the CPU exposes each component’s size and offset based on its feature number, making it a key for state information. To provide flexibility in handling xstate ordering, introduce a mapping table: feature order -> feature number. The table is dynamically populated based on the CPU-exposed features and is sorted in offset order at boot time. Additionally, add an accessor macro to facilitate sequential traversal of xstate components based on their actual buffer positions, given a feature bitmask. This accessor macro will be particularly useful for computing custom non-compacted format sizes and iterating over xstate offsets in non-compacted buffers. Intel-SIG: commit 15d51a2f6f3f x86/fpu/xstate: Introduce xfeature order table and accessor macro. DMR ISA APX enabling - HOST Suggested-by: Dave Hansen <dave.hansen@linux.intel.com> Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Andy Lutomirski <luto@kernel.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Link: https://lore.kernel.org/r/20250320234301.8342-3-chang.seok.bae@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit a758ae2885eacaa68e4de9a01539a242a6bbb403 upstream. The current xstate size calculation assumes that the highest-numbered xstate feature has the highest offset in the buffer, determining the size based on the topmost bit in the feature mask. However, this assumption is not architecturally guaranteed -- higher-numbered features may have lower offsets. With the introduction of the xfeature order table and its helper macro, xstate components can now be traversed in their positional order. Update the non-compacted format handling to iterate through the table to determine the last-positioned feature. Then, set the offset accordingly. Since size calculation primarily occurs during initialization or in non-critical paths, looping to find the last feature is not expected to have a meaningful performance impact. Intel-SIG: commit a758ae2885ea x86/fpu/xstate: Adjust XSAVE buffer size calculation. DMR ISA APX enabling - HOST Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Andy Lutomirski <luto@kernel.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Link: https://lore.kernel.org/r/20250320234301.8342-4-chang.seok.bae@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit cbe8e4dab16c56ac84765dcd53e418160c8bc0db upstream. == Background == As feature positions in the userspace XSAVE buffer do not always align with their feature numbers, the XSAVE format conversion needs to be reconsidered to align with the revised xstate size calculation logic. * For signal handling, XSAVE and XRSTOR are used directly to save and restore extended registers. * For ptrace, KVM, and signal returns (for 32-bit frame), the kernel copies data between its internal buffer and the userspace XSAVE buffer. If memcpy() were used for these cases, existing offset helpers — such as __raw_xsave_addr() or xstate_offsets[] — would be sufficient to handle the format conversion. == Problem == When copying data from the compacted in-kernel buffer to the non-compacted userspace buffer, the function follows the user_regset_get2_fn() prototype. This means it utilizes struct membuf helpers for the destination buffer. As defined in regset.h, these helpers update the memory pointer during the copy process, enforcing sequential writes within the loop. Since xstate components are processed sequentially, any component whose buffer position does not align with its feature number has an issue. == Solution == Replace for_each_extended_xfeature() with the newly introduced for_each_extended_xfeature_in_order(). This macro ensures xstate components are handled in the correct order based on their actual positions in the destination buffer, rather than their feature numbers. Intel-SIG: commit cbe8e4dab16c x86/fpu/xstate: Adjust xstate copying logic for user ABI. DMR ISA APX enabling - HOST Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Andy Lutomirski <luto@kernel.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Link: https://lore.kernel.org/r/20250320234301.8342-5-chang.seok.bae@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit b02dc185ee86836cf1d8a37b81349374e4018ee0 upstream. Intel Advanced Performance Extensions (APX) introduce a new set of general-purpose registers, managed as an extended state component via the xstate management facility. Before enabling this new xstate, define a feature flag to clarify the dependency in xsave_cpuid_features[]. APX is enumerated under CPUID level 7 with EDX=1. Since this CPUID leaf is not yet allocated, place the flag in a scattered feature word. While this feature is intended only for userspace, exposing it via /proc/cpuinfo is unnecessary. Instead, the existing arch_prctl(2) mechanism with the ARCH_GET_XCOMP_SUPP option can be used to query the feature availability. Finally, clarify that APX depends on XSAVE. Intel-SIG: commit b02dc185ee86 x86/cpufeatures: Add X86_FEATURE_APX. DMR ISA APX enabling - HOST Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Sohil Mehta <sohil.mehta@intel.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Link: https://lore.kernel.org/r/20250416021720.12305-2-chang.seok.bae@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit bd0b10b795c5c4c587e83c0498251356874c655c upstream. Advanced Performance Extensions (APX) is associated with a new state component number 19. To support saving and restoring of the corresponding registers via the XSAVE mechanism, introduce the component definition along with the necessary sanity checks. Define the new component number, state name, and those register data type. Then, extend the size checker to validate the register data type and explicitly list the APX feature flag as a dependency for the new component in xsave_cpuid_features[]. Intel-SIG: commit bd0b10b795c5 x86/fpu/apx: Define APX state component. DMR ISA APX enabling - HOST Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Sohil Mehta <sohil.mehta@intel.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Link: https://lore.kernel.org/r/20250416021720.12305-3-chang.seok.bae@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit ea68e39190cff86f457bd286c70b535e2a99a94d upstream.
XSTATE components are architecturally independent. There is no rule
requiring their offsets in the non-compacted format to be strictly
ascending or mutually non-overlapping. However, in practice, such
overlaps have not occurred -- until now.
APX is introduced as xstate component 19, following AMX. In the
non-compacted XSAVE format, its offset overlaps with the space previously
occupied by the now-deprecated MPX feature:
45fc24e ("x86/mpx: remove MPX from arch/x86")
To prevent conflicts, the kernel must ensure the CPU never expose both
features at the same time. If so, it indicates unreliable hardware. In
such cases, XSAVE should be disabled entirely as a precautionary measure.
Add a sanity check to detect this condition and disable XSAVE if an
invalid hardware configuration is identified.
Note: MPX state components remain enabled on legacy systems solely for
KVM guest support.
Intel-SIG: commit ea68e39190cf x86/fpu/apx: Disallow conflicting MPX presence.
DMR ISA APX enabling - HOST
Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Sohil Mehta <sohil.mehta@intel.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Link: https://lore.kernel.org/r/20250416021720.12305-4-chang.seok.bae@intel.com
[ Quanxian Wang: amend commit log ]
Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit 50c5b071e2833d2b61e3774cd792620311df157c upstream. With securing APX against conflicting MPX, it is now ready to be enabled. Include APX in the enabled xfeature set. Intel-SIG: commit 50c5b071e283 x86/fpu/apx: Enable APX state support. DMR ISA APX enabling - HOST Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Sohil Mehta <sohil.mehta@intel.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Link: https://lore.kernel.org/r/20250416021720.12305-5-chang.seok.bae@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit ab6f87ddd0c6d3fb114cdf897eb9839cbd429439 upstream. The extended general-purpose registers for APX may contain random data, which is currently assumed by the xstate testing framework. This allows the testing of the new userspace feature using the common test code. Invoke the test entry function from apx.c after enumerating the state component and adding it to the support list Intel-SIG: commit ab6f87ddd0c6 selftests/x86/apx: Add APX test. DMR ISA APX enabling - HOST Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Sohil Mehta <sohil.mehta@intel.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Link: https://lore.kernel.org/r/20250416021720.12305-6-chang.seok.bae@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit 39cd7fad39ce2ffbeb21939c805ee55f3ec808d4 upstream. Not all paths that lead to fpu__init_disable_system_xstate() currently emit a message indicating that XSAVE has been disabled. Move the print statement into the function to ensure the message in all cases. Intel-SIG: commit 39cd7fad39ce x86/fpu: Log XSAVE disablement consistently. DMR ISA APX enabling - HOST Suggested-by: Dave Hansen <dave.hansen@linux.intel.com> Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Andy Lutomirski <luto@kernel.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Link: https://lore.kernel.org/r/20250416021720.12305-7-chang.seok.bae@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit 64e54461ab6e8524a8de4e63b7d1a3e4481b5cf3 upstream. Currently, saving register states in the signal frame, the legacy feature bits are always set in xregs_state->header->xfeatures. This code sequence can be generalized for reuse in similar cases. Refactor the logic to ensure a consistent approach across similar usages. Intel-SIG: commit 64e54461ab6e x86/fpu: Refactor xfeature bitmask update code for sigframe XSAVE. DMR ISA APX enabling - HOST Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Andy Lutomirski <luto@kernel.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Link: https://lore.kernel.org/r/20250416021720.12305-8-chang.seok.bae@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit d1e420772cd1eb0afe5858619c73ce36f3e781a1 upstream.
The signal delivery logic was modified to always set the PKRU bit in
xregs_state->header->xfeatures by this commit:
ae6012d72fa6 ("x86/pkeys: Ensure updated PKRU value is XRSTOR'd")
However, the change derives the bitmask value using XGETBV(1), rather
than simply updating the buffer that already holds the value. Thus, this
approach induces an unnecessary dependency on XGETBV1 for PKRU handling.
Eliminate the dependency by using the established helper function.
Subsequently, remove the now-unused 'mask' argument.
Intel-SIG: commit d1e420772cd1 x86/pkeys: Simplify PKRU update in signal frame.
DMR ISA APX enabling - HOST
Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Aruna Ramakrishna <aruna.ramakrishna@oracle.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Link: https://lore.kernel.org/r/20250416021720.12305-9-chang.seok.bae@intel.com
[ Quanxian Wang: amend commit log ]
Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit 70fe4a0266ef156f3a49071da0d9ea6af0f49c44 upstream.
The variable was previously referenced in KVM code but the last usage was
removed by:
ea4d693 ("x86/fpu: Replace KVMs home brewed FPU copy from user")
Remove its export symbol.
Intel-SIG: commit 70fe4a0266ef x86/fpu: Remove export of mxcsr_feature_mask.
DMR ISA APX enabling - HOST
Reviewed-by: Nikolay Borisov <nik.borisov@suse.com>
Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Link: https://lore.kernel.org/r/20250416021720.12305-10-chang.seok.bae@intel.com
[ Quanxian Wang: amend commit log ]
Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit de8304c319bc020ef79d109909ad40e944d82c82 upstream.
The original function name came from an overly compressed form of
'fpstate_regs' by commit:
e61d631 ("x86/fpu: Reset permission and fpstate on exec()")
However, the term 'fpregs' typically refers to physical FPU registers. In
contrast, this function copies the init values to fpu->fpstate->regs, not
hardware registers.
Rename the function to better reflect what it actually does.
No functional change.
Intel-SIG: commit de8304c319bc x86/fpu: Rename fpu_reset_fpregs() to fpu_reset_fpstate_regs().
DMR ISA APX enabling - HOST
Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Link: https://lore.kernel.org/r/20250416021720.12305-11-chang.seok.bae@intel.com
[ Quanxian Wang: amend commit log ]
Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit d222b6e6fb31e320eca506e665694d8ddf459157 upstream.
To pick the changes from:
faad6645e1128ec2 ("x86/cpufeatures: Add CPUID feature bit for the Bus Lock Threshold")
159013a7ca18c271 ("x86/its: Enumerate Indirect Target Selection (ITS) bug")
f9f27c4a377a8b45 ("x86/cpufeatures: Add "Allowed SEV Features" Feature")
b02dc185ee86836c ("x86/cpufeatures: Add X86_FEATURE_APX")
d88bb2ded2efdc38 ("KVM: x86: Advertise support for AMD's PREFETCHI")
This causes these perf files to be rebuilt and brings some X86_FEATURE
that may be used by:
CC /tmp/build/perf/bench/mem-memcpy-x86-64-asm.o
CC /tmp/build/perf/bench/mem-memset-x86-64-asm.o
And addresses this perf build warning:
Warning: Kernel ABI header differences:
diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h
Please see tools/include/uapi/README for further details.
Intel-SIG: commit d222b6e6fb31 tools headers x86 cpufeatures: Sync with the kernel sources.
DMR ISA APX enabling - HOST
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Babu Moger <babu.moger@amd.com>
Cc: Chang S. Bae <chang.seok.bae@intel.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: James Clark <james.clark@linaro.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Kishon Vijay Abraham I <kvijayab@amd.com>
Cc: Manali Shukla <manali.shukla@amd.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Cc: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/aFBWAI3kHYX5aL9G@x1
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
[ Quanxian Wang: amend commit log ]
Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
quanxianwang
force-pushed
the
DMR-APX
branch
from
d73c98d to
556c5dc
Compare
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
5 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
APX ISA support
Intel® Advanced Performance Extensions (Intel® APX) expands the entire x86 instruction set with access to more registers and adds new features that improve general-purpose performance. The extensions provide efficient performance gains across a variety of workloads without significantly increasing the silicon area or power consumption of the core.
A set of new integer registers – 16 64-bit GPRs (r16-r31). That register state is XSAVE-ed for efficient context switching. there are 3 parts to support APX, this patchset is for APX host. Another two includes kvm (still under review), and qemu part for client APX support.
APX host support including (appendix A for patch lists)
PART1-depenency: xstate selftest support AVX
PART2: XSTATE Code Adjustment
PART3: APX Enabling
Testing: PASS on DMR simics
Testing Details: (selftest)
"# ./tools/testing/selftests/x86/apx_64"
[RUN] APX registers: check context switches, 10 iterations, 5 threads.
[OK] No incorrect case was found.
[RUN] APX registers: inject xstate via ptrace().
[OK] 'xfeatures' in SW reserved area was correctly written
[OK] xstate was correctly updated.
[RUN] APX registers: load xstate and raise SIGUSR1
[OK] 'magic1' is valid
[OK] 'xfeatures' in SW reserved area is valid
[OK] 'xfeatures' in XSAVE header is valid
[OK] xstate delivery was successful
[OK] 'magic2' is valid
[RUN] APX registers: load new xstate from sighandler and check it after sigreturn
[OK] xstate was restored correctly
Appendix A - patch series (totally 31 commits including dependency)
d222b6e6fb31,tools headers x86 cpufeatures: Sync with the kernel sources,2025-06-16 14:18:55,Arnaldo Carvalho de Melo acme@redhat.com,v6.16-rc3 -- fixes of b02dc185ee86
'## APX feature enabling'
de8304c319bc,x86/fpu: Rename fpu_reset_fpregs() to fpu_reset_fpstate_regs(),2025-04-16 10:01:03,Chang S. Bae chang.seok.bae@intel.com,v6.16-rc1,BP-BY-Chang S. Bae chang.seok.bae@intel.com
70fe4a0266ef,x86/fpu: Remove export of mxcsr_feature_mask,2025-04-16 10:01:03,Chang S. Bae chang.seok.bae@intel.com,v6.16-rc1,BP-BY-Chang S. Bae chang.seok.bae@intel.com
d1e420772cd1,x86/pkeys: Simplify PKRU update in signal frame,2025-04-16 10:01:03,Chang S. Bae chang.seok.bae@intel.com,v6.16-rc1,BP-BY-Chang S. Bae chang.seok.bae@intel.com
'# dependency of d1e420772cd1'
ae6012d72fa6,x86/pkeys: Ensure updated PKRU value is XRSTOR'd,2024-12-02 15:25:29,Aruna Ramakrishna aruna.ramakrishna@oracle.com,v6.13-rc2 - dependency of d1e420772cd1
64e54461ab6e,x86/fpu: Refactor xfeature bitmask update code for sigframe XSAVE,2025-04-16 10:01:00,Chang S. Bae chang.seok.bae@intel.com,v6.16-rc1,BP-BY-Chang S. Bae chang.seok.bae@intel.com
39cd7fad39ce,x86/fpu: Log XSAVE disablement consistently,2025-04-16 09:44:15,Chang S. Bae chang.seok.bae@intel.com,v6.16-rc1,BP-BY-Chang S. Bae chang.seok.bae@intel.com
ab6f87ddd0c6,selftests/x86/apx: Add APX test,2025-04-16 09:44:14,Chang S. Bae chang.seok.bae@intel.com,v6.16-rc1,BP-BY-Chang S. Bae chang.seok.bae@intel.com
50c5b071e283,x86/fpu/apx: Enable APX state support,2025-04-16 09:44:14,Chang S. Bae chang.seok.bae@intel.com,v6.16-rc1,BP-BY-Chang S. Bae chang.seok.bae@intel.com
ea68e39190cf,x86/fpu/apx: Disallow conflicting MPX presence,2025-04-16 09:44:14,Chang S. Bae chang.seok.bae@intel.com,v6.16-rc1,BP-BY-Chang S. Bae chang.seok.bae@intel.com
bd0b10b795c5,x86/fpu/apx: Define APX state component,2025-04-16 09:44:14,Chang S. Bae chang.seok.bae@intel.com,v6.16-rc1,BP-BY-Chang S. Bae chang.seok.bae@intel.com
b02dc185ee86,x86/cpufeatures: Add X86_FEATURE_APX,2025-04-16 09:44:13,Chang S. Bae chang.seok.bae@intel.com,v6.16-rc1
#dependency d1e420772cd1 depends on 84ee6e8, 6a1853bdf178
6a1853bdf178,x86/pkeys: Change caller of update_pkru_in_sigframe(),2024-11-19 17:45:19,Aruna Ramakrishna aruna.ramakrishna@oracle.com,v6.13-rc2
84ee6e8,x86/pkeys: Add helper functions to update PKRU on the sigframe,2024-08-02 06:13:15,Aruna Ramakrishna aruna.ramakrishna@oracle.com,v6.12-rc1
'#'
'## XSTATE updates'
'#'
cbe8e4dab16c,x86/fpu/xstate: Adjust xstate copying logic for user ABI,2025-04-14 08:18:29,Chang S. Bae chang.seok.bae@intel.com,v6.16-rc1,v6.16-rc1
a758ae2885ea,x86/fpu/xstate: Adjust XSAVE buffer size calculation,2025-04-14 08:18:29,Chang S. Bae chang.seok.bae@intel.com,v6.16-rc1,v6.16-rc1
15d51a2f6f3f,x86/fpu/xstate: Introduce xfeature order table and accessor macro,2025-04-14 08:18:29,Chang S. Bae chang.seok.bae@intel.com,v6.16-rc1,v6.16-rc1
031b33ef1a6a,x86/fpu/xstate: Remove xstate offset check,2025-04-14 08:18:29,Chang S. Bae chang.seok.bae@intel.com,v6.16-rc1,v6.16-rc1
69a2fdf44604,x86/fpu/xstate: Simplify print_xstate_features(),2025-02-27 19:54:41,Chang S. Bae chang.seok.bae@intel.com,v6.15-rc1,v6.15-rc1
'# xstate selftest which support AVX tests'
'# patch set of bfc98dbcb3c7 ("selftests/x86/avx: Add AVX tests")'
bfc98dbcb3c7,selftests/x86/avx: Add AVX tests,2025-02-26 13:05:30,Chang S. Bae chang.seok.bae@intel.com,v6.15-rc1,v6.15-rc1
fa826c1f2cc9,selftests/x86/xstate: Clarify supported xstates,2025-02-26 13:05:30,Chang S. Bae chang.seok.bae@intel.com,v6.15-rc1,v6.15-rc1
10d8a204c500,selftests/x86/xstate: Consolidate test invocations into a single entry,2025-02-26 13:05:29,Chang S. Bae chang.seok.bae@intel.com,v6.15-rc1,v6.15-rc1
e075d9fa16b3,selftests/x86/xstate: Introduce signal ABI test,2025-02-26 13:05:29,Chang S. Bae chang.seok.bae@intel.com,v6.15-rc1,v6.15-rc1
7cb2fbe41949,selftests/x86/xstate: Refactor ptrace ABI test,2025-02-26 13:05:29,Chang S. Bae chang.seok.bae@intel.com,v6.15-rc1,v6.15-rc1
40f6852ef2bf,selftests/x86/xstate: Refactor context switching test,2025-02-26 13:05:29,Chang S. Bae chang.seok.bae@intel.com,v6.15-rc1,v6.15-rc1
3fcb4d614656,selftests/x86/xstate: Enumerate and name xstate components,2025-02-26 13:05:28,Chang S. Bae chang.seok.bae@intel.com,v6.15-rc1,v6.15-rc1
0f6d91a327db,selftests/x86/xstate: Refactor XSAVE helpers for general use,2025-02-26 13:05:28,Chang S. Bae chang.seok.bae@intel.com,v6.15-rc1,v6.15-rc1
dbd6b649e7d5,selftests/x86: Consolidate redundant signal helper functions,2025-02-26 13:05:28,Chang S. Bae chang.seok.bae@intel.com,v6.15-rc1,v6.15-rc1
'## dependency for selftest apx_64, avx_64, amx_64'
825658b,selftests/x86: fix Makefile dependencies to work with clang,2024-07-11 11:23:54,John Hubbard jhubbard@nvidia.com,v6.11-rc1
dependency of 0f6d91a327db
99c8431,x86/selftests: Skip the tests if prerequisites aren't fulfilled,2024-03-29 08:33:40,Muhammad Usama Anjum usama.anjum@collabora.com,v6.10-rc1