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commit 5ee8009 upstream. New CPU #defines encode vendor and family as well as model. Intel-SIG: commit 5ee8009 perf/x86/intel/cstate: Switch to new Intel CPU model defines Backport cstate PMU for CWF Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Link: https://lore.kernel.org/all/20240424181459.41500-1-tony.luck%40intel.com [ Zhang Rui: amend commit log ] Signed-off-by: Zhang Rui <rui.zhang@intel.com>
commit dc8e5df upstream. Fix the 'make W=1 C=1' warnings: WARNING: modpost: missing MODULE_DESCRIPTION() in arch/x86/events/intel/intel-uncore.o WARNING: modpost: missing MODULE_DESCRIPTION() in arch/x86/events/intel/intel-cstate.o Intel-SIG: commit dc8e5df perf/x86/intel: Add missing MODULE_DESCRIPTION() lines Backport cstate PMU for CWF Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Link: https://lore.kernel.org/r/20240530-md-arch-x86-events-intel-v1-1-8252194ed20a@quicinc.com [ Zhang Rui: amend commit log ] Signed-off-by: Zhang Rui <rui.zhang@intel.com>
commit b1d0e15 upstream. Package C2 residency counter is also available on Sierra Forest. So add it support in srf_cstates. Intel-SIG: commit b1d0e15 perf/x86/intel/cstate: Add pkg C2 residency counter for Sierra Forest Backport cstate PMU for CWF Fixes: 3877d55 ("perf/x86/intel/cstate: Add Sierra Forest support") Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Tested-by: Wendy Wang <wendy.wang@intel.com> Link: https://lore.kernel.org/r/20240717031609.74513-1-zhenyuw@linux.intel.com [ Zhang Rui: amend commit log ] Signed-off-by: Zhang Rui <rui.zhang@intel.com>
commit e39b82f6cb0526c551d4651ba6d286b6b1f9e9c3 upstream. Clearwater Forest is based on the Darkmont Atom microarchitecture. >From the perspective of C-state residency profiling, it supports the same residency counters as Sierra Forest: CC1/CC6, PC2/PC6, and MC6. Please note that the C1E residency counter can only be read via PMT, not MSR. Therefore, tools relying on the perf_event framework cannot access the C1E residency. Intel-SIG: commit e39b82f6cb05 perf/x86/intel/cstate: Add Clearwater Forest support Backport cstate PMU for CWF Signed-off-by: Zhenyu Wang <zhenyuw.linux@gmail.com> Signed-off-by: Zide Chen <zide.chen@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Link: https://patch.msgid.link/20251023223754.1743928-2-zide.chen@intel.com [ Zhang Rui: amend commit log ] Signed-off-by: Zhang Rui <rui.zhang@intel.com>
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Backport cstate PMU for CWF. Switch to new Intel CPU model defines and add SRF PC2 support at the same time.
Test:
Tested on SRF/GNR/CWF,
On SRF, perf event "cstate_pkg/c2-residency/" becomes available with this PR.
On CWF, perf events "cstate_core/c1-residency/ cstate_core/c6-residency/ cstate_module/c6-residency/ cstate_pkg/c2-residency/ cstate_pkg/c6-residency" become available with this PR.
On GNR, no regression found.