Merge pull request #487 from davidharrishmc/dev

Zalrsc 100%, clean up custom instruction and CSR coverage

fcov/priv/ExceptionsZc_coverage.svh

@@ -85,16 +85,29 @@ covergroup ExceptionsZc_instr_cg with function sample(ins_t ins);
         // exhaustive test of 2^14 compressed instructions with op = 01 with following exceptions that would be hard to test
         bins c01[] = {[0:14'b00011111111111]};
         ignore_bins c_jal = {[14'b00100000000000:14'b00111111111111]};
-        bins c01b[] = {[14'b01000000000000:14'b10011111111111]};
+        bins c01b[] = {[14'b01000000000000:14'b10001_111111111]};
+        `ifdef XLEN32
+            ignore_bins c_srli_srai_custom = {[14'b10010_000000000:14'b10010_111111111]}; // reserved for custom use in RV32Zca; behavior is unpredictable
+        `else
+            bins c_srli_srai_rv64[] = {[14'b10010_000000000:14'b10010_111111111]}; // RV64Zca c.srli/srai with shift amount of 32-63
+        `endif
+        bins c01c[] = {[14'b10011_000000000:14'b10011_111111111]};
         ignore_bins c_j = {[14'b10100000000000:14'b10111111111111]};
         ignore_bins c_bez_bez = {[14'b11000000000000:14'b11111111111111]};
      }
     cp_compressed10 : coverpoint ins.current.insn[15:2] iff (ins.current.insn[1:0] == 2'b10) {
         // exhaustive test of 2^14 compressed instructions with op = 10
-        bins c10a[] = {[0:14'b01111111111111]};
+        //bins c10a[] = {[0:14'b01111111111111]};
+        bins c10a[] = {[0:14'b0000_1111111111]};
+        `ifdef XLEN32
+            ignore_bins c_slii_custom = {[14'b0001_0000000000:14'b0001_1111111111]}; // reserved for custom use in RV32Zca; behavior is unpredictable
+        `else
+            bins c_slli_rv64[] = {[14'b0001_0000000000:14'b0001_1111111111]}; // RV64Zca c.slli with shift amount of 32-63
+        `endif
+        bins c10b[] = {[14'b001_00000000000:14'b01111111111111]};
         ignore_bins c_jr = {[14'b10000000000000:14'b10001111111111]};
         ignore_bins c_jalr = {[14'b10010000000000:14'b10011111111111]};
-        bins c10b[] = {[14'b10100000000000:$]};
+        bins c10c[] = {[14'b10100000000000:$]};
     }
 endgroup
 

fcov/priv/ZicsrM_coverage.svh

@@ -44,7 +44,8 @@ covergroup ZicsrM_mcsr_cg with function sample(ins_t ins);
         bins hyper_std1[] = {[12'h600:12'h6BF]};
         ignore_bins hyper_custom1[] = {[12'h6C0:12'h6FF]};
         bins mach_std1[] = {[12'h700:12'h7AF]};
-        ignore_bins mach_debug[] = {[12'h7B0:12'h7BF]}; // toggling debug registers could do weird stuff
+        ignore_bins mach_debug[] = {[12'h7A0:12'h7AF]}; // toggling debug registers could do weird stuff
+        bins debug_only[] = {[12'h7B0:12'h7BF]}; // access to debug mode registers raises illegal instruction even in machine mode
         ignore_bins mach_custom1[] = {[12'h7C0:12'h7FF]};
         ignore_bins user_custom2[] = {[12'h800:12'h8FF]};
         bins super_std2[] = {[12'h900:12'h9BF]};

fcov/priv/ZicsrS_coverage.svh

@@ -35,8 +35,36 @@ covergroup ZicsrS_scsr_cg with function sample(ins_t ins);
     csrrw: coverpoint ins.current.insn {
         wildcard bins csrrw = {32'b????????????_?????_001_?????_1110011}; 
     }
+    // csr is similar to in ZicsrM, but also exercises custom/debug machine mode CSRs, which should trap from supervisor level
     csr: coverpoint ins.current.insn[31:20]  {
-        bins all[] = {[0:$]};
+        bins user_std0[] = {[12'h000:12'h0FF]};
+        bins super_std0[] = {[12'h100:12'h1FF]};
+        bins hyper_std0[] = {[12'h200:12'h2FF]};
+        bins mach_std0[] = {[12'h300:12'h3FF]};
+        bins user_std1[] = {[12'h400:12'h4FF]};
+        bins super_std1[] = {[12'h500:12'h5BF]};
+        ignore_bins super_custom1[] = {[12'h5C0:12'h5FF]};
+        bins hyper_std1[] = {[12'h600:12'h6BF]};
+        ignore_bins hyper_custom1[] = {[12'h6C0:12'h6FF]};
+        bins mach_std1[] = {[12'h700:12'h7AF]};
+        bins mach_debug[] = {[12'h7A0:12'h7AF]}; // toggling debug registers could do weird stuff
+        bins debug_only[] = {[12'h7B0:12'h7BF]}; // access to debug mode registers raises illegal instruction even in machine mode
+        bins mach_custom1[] = {[12'h7C0:12'h7FF]};
+        ignore_bins user_custom2[] = {[12'h800:12'h8FF]};
+        bins super_std2[] = {[12'h900:12'h9BF]};
+        ignore_bins super_custom22[] = {[12'h9C0:12'h9FF]};
+        bins hyper_std2[] = {[12'hA00:12'hABF]};
+        ignore_bins hyper_custom22[] = {[12'hAC0:12'hAFF]};
+        bins mach_std2[] = {[12'hB00:12'hBBF]};
+        bins mach_custom2[] = {[12'hBC0:12'hBFF]};
+        bins user_std3[] = {[12'hC00:12'hCBF]};
+        ignore_bins user_custom3[] = {[12'hCC0:12'hCFF]};
+        bins super_std3[] = {[12'hD00:12'hDBF]};
+        ignore_bins super_custom3[] = {[12'hDC0:12'hDFF]};
+        bins hyper_std3[] = {[12'hE00:12'hEBF]};
+        ignore_bins hyper_custom3[] = {[12'hEC0:12'hEFF]};
+        bins mach_std3[] = {[12'hF00:12'hFBF]};
+        bins mach_custom3[] = {[12'hFC0:12'hFFF]};
     }
     csr_no_satp: coverpoint ins.current.insn[31:20]  {
         bins all[] = {[0:$]};

fcov/priv/ZicsrU_coverage.svh

@@ -37,8 +37,36 @@ covergroup ZicsrU_ucsr_cg with function sample(ins_t ins);
     csrrw: coverpoint ins.current.insn {
         wildcard bins csrrw = {32'b????????????_?????_001_?????_1110011}; 
     }
+   // csr is similar to in ZicsrM, but also exercises custom/debug machine/supervisor mode CSRs, which should trap from user level
     csr: coverpoint ins.current.insn[31:20]  {
-        bins all[] = {[0:$]};
+        bins user_std0[] = {[12'h000:12'h0FF]};
+        bins super_std0[] = {[12'h100:12'h1FF]};
+        bins hyper_std0[] = {[12'h200:12'h2FF]};
+        bins mach_std0[] = {[12'h300:12'h3FF]};
+        bins user_std1[] = {[12'h400:12'h4FF]};
+        bins super_std1[] = {[12'h500:12'h5BF]};
+        bins super_custom1[] = {[12'h5C0:12'h5FF]};
+        bins hyper_std1[] = {[12'h600:12'h6BF]};
+        bins hyper_custom1[] = {[12'h6C0:12'h6FF]};
+        bins mach_std1[] = {[12'h700:12'h7AF]};
+        bins mach_debug[] = {[12'h7A0:12'h7AF]}; // toggling debug registers could do weird stuff
+        bins debug_only[] = {[12'h7B0:12'h7BF]}; // access to debug mode registers raises illegal instruction even in machine mode
+        bins mach_custom1[] = {[12'h7C0:12'h7FF]};
+        ignore_bins user_custom2[] = {[12'h800:12'h8FF]};
+        bins super_std2[] = {[12'h900:12'h9BF]};
+        bins super_custom22[] = {[12'h9C0:12'h9FF]};
+        bins hyper_std2[] = {[12'hA00:12'hABF]};
+        bins hyper_custom22[] = {[12'hAC0:12'hAFF]};
+        bins mach_std2[] = {[12'hB00:12'hBBF]};
+        bins mach_custom2[] = {[12'hBC0:12'hBFF]};
+        bins user_std3[] = {[12'hC00:12'hCBF]};
+        ignore_bins user_custom3[] = {[12'hCC0:12'hCFF]};
+        bins super_std3[] = {[12'hD00:12'hDBF]};
+        bins super_custom3[] = {[12'hDC0:12'hDFF]};
+        bins hyper_std3[] = {[12'hE00:12'hEBF]};
+        bins hyper_custom3[] = {[12'hEC0:12'hEFF]};
+        bins mach_std3[] = {[12'hF00:12'hFBF]};
+        bins mach_custom3[] = {[12'hFC0:12'hFFF]};
     }
     priv_mode_u: coverpoint ins.current.mode {
         bins U_mode = {2'b00};

templates/coverage/cp_custom_lr.txt

@@ -2,3 +2,14 @@
         // Combinations of acquire and release
         ignore_bins rl_noaq = {2'b01};
     }
+    cp_custom_rd_corners : coverpoint ins.current.rd_val iff (ins.trap == 0) {
+        `ifdef XLEN32
+            bins zero = {0};
+            bins one  = {32'b00000000000000000000000000000001};
+            bins max  = {32'b11111111111111111111111111111111};
+        `else // XLEN64
+            bins zero = {0};
+            bins one  = {64'b0000000000000000000000000000000000000000000000000000000000000001};
+            bins max  = {64'b1111111111111111111111111111111111111111111111111111111111111111};
+        `endif
+    }

templates/coverage/cp_custom_sc.txt

@@ -1,7 +1,10 @@
     // Custom coverpoints for Store Conditional
 
-    cp_prev_lr : coverpoint (ins.prev.inst_name == "lr.w" | ins.prev.inst_name == "lr.d") {
-        // previous instruction was load reserved
+    cp_prev_lr : coverpoint ({ins.prev.inst_name == "lr.w", ins.prev.inst_name == "lr.d"}) {
+        bins lr_w = {2'b10};  // previous instruction was load reserved
+        `ifdef XLEN64
+            bins lr_d = {2'b01};
+        `endif
     }
 
     cp_sc_fail : coverpoint (ins.current.rd_val) {
@@ -30,6 +33,17 @@
         `endif
         wildcard ignore_bins badbin = {3'b1??};
     }
+    cp_custom_sc_after_load : coverpoint (ins.prev.insn[14:12]) iff (ins.prev.insn[6:0] == 7'b0000011) {
+        // previous instruction was a store
+        bins lb  = {3'b000};
+        bins lh  = {3'b001};
+        bins lhu = {3'b101};
+        bins lw  = {3'b010};
+        `ifdef XLEN64
+            bins lwu = {3'b110};
+            bins ld  = {3'b011};
+        `endif
+    }
     cp_custom_sc_lrsc : cross cp_prev_lr, cp_sc_fail;
     cp_custom_sc_addresses : cross cp_prev_lr, cp_address_difference;
 

templates/testgen/lr.d.S

@@ -10,5 +10,19 @@
     lr.d.aq t2, (t0)
     lr.d.aqrl t3, (t0)
 
-
+# cp_custom_rd_corners 
+    li t4, 0x0  
+    sd t4, 0(t0)
+    lr.d t1, (t0)   # lr t1 = 0
 
+    li t4, 0x1
+    sd t4, 0(t0)
+    lr.d t1, (t0)   # lr t1 = 1
+
+    li t4, 0x00000000FFFFFFFF
+    sd t4, 0(t0)
+    lr.d t1, (t0)   # lr t1 = 00000000FFFFFFFF
+
+    li t4, 0xFFFFFFFFFFFFFFFF
+    sd t4, 0(t0)
+    lr.d t1, (t0)   # lr t1 = FFFFFFFFFFFFFFFF

templates/testgen/lr.w.S

@@ -10,5 +10,17 @@
     lr.w.aq t2, (t0)
     lr.w.aqrl t3, (t0)
 
-
+   # cp_custom_rd_corners 
+    li t4, 0x0  
+    sw t4, 0(t0)
+    sw zero, 4(t0)
+    lr.w t1, (t0)   # lr t1 = 0
+
+    li t4, 0x1
+    sw t4, 0(t0)
+    lr.w t1, (t0)   # lr t1 = 1
+
+    li t4, 0xFFFFFFFF
+    sw t4, 0(t0)
+    lr.w t1, (t0)   # lr t1 = FFFFFFFF (sign-extended in RV64)
 

templates/testgen/sc.d.S

@@ -39,6 +39,17 @@
     lr.d t1, (t0)       # load from reservation set
     sc.d t1, t3, (t5)   # try store conditional, should succeed if in same set
     sc.d t1, t3, (t5)   # try again, and it should fail this time
+
+    # for RV64, also check different size lr vs. sc
+    #ifdef __riscv_xlen
+        #if __riscv_xlen == 64
+            lr.w t1, (t0)
+            sc.d t1, t3, (t5)
+         #endif
+    #else
+        ERROR: __riscv_xlen not defined
+    #endif
+
     addi t6, t6, 8      # increment offset
     slti t5, t6, 129    # offset <= 128
     bnez t5, 1b         # repeat until done
@@ -60,3 +71,69 @@
     lr.d t1, (t0)
     sd t3, 0(t0)      # store double
     sc.d t5, t4, (t0) # succeeds
+
+# cp_custom_sc_after_load
+    # should not care about intervening loads
+
+    lr.w t1, (t0)
+    lb t3, 3(t0)      # load byte
+    sc.d t5, t4, (t0) # succeeds
+
+    lr.w t1, (t0)
+    lb t3, 128(t0)      # load byte
+    sc.d t5, t4, (t0) # succeeds
+
+    lr.w t1, (t0)
+    lbu t3, 2(t0)      # load byte unsigned
+    sc.d t5, t4, (t0) # succeeds
+
+    lr.w t1, (t0)
+    lbu t3, 128(t0)      # load byte unsigned
+    sc.d t5, t4, (t0) # succeeds
+
+    lr.w t1, (t0)
+    lh t3, 2(t0)      # load half
+    sc.d t5, t4, (t0) # succeeds
+
+    lr.w t1, (t0)
+    lh t3, 128(t0)      # load half
+    sc.d t5, t4, (t0) # succeeds
+
+    lr.w t1, (t0)
+    lhu t3, 0(t0)      # load half unsigned
+    sc.d t5, t4, (t0) # succeeds
+
+    lr.w t1, (t0)
+    lhu t3, 128(t0)      # load half unsigned
+    sc.d t5, t4, (t0) # succeeds
+
+    lr.w t1, (t0)
+    lw t3, 0(t0)      # load word
+    sc.d t5, t4, (t0) # succeeds
+
+    lr.w t1, (t0)
+    lw t3, 128(t0)      # load word
+    sc.d t5, t4, (t0) # succeeds
+
+    #ifdef __riscv_xlen
+        #if __riscv_xlen == 64
+            lr.w t1, (t0)
+            lwu t3, 0(t0)      # load word unsigned
+            sc.d t5, t4, (t0) # succeeds
+
+            lr.w t1, (t0)
+            lwu t3, 128(t0)      # load word unsigned
+            sc.d t5, t4, (t0) # succeeds
+
+            lr.w t1, (t0)
+            ld t3, 0(t0)      # load double
+            sc.d t5, t4, (t0) # succeeds
+
+            lr.w t1, (t0)
+            ld t3, 128(t0)      # load double
+            sc.d t5, t4, (t0) # succeeds
+
+        #endif
+    #else
+        ERROR: __riscv_xlen not defined
+    #endif

templates/testgen/sc.w.S

@@ -30,6 +30,17 @@
     lr.w t1, (t0)       # load from reservation set
     sc.w t1, t3, (t5)   # try store conditional, should succeed if in same set
     sc.w t1, t3, (t5)   # try again, and it should fail this time
+
+    # for RV64, also check different size lr vs. sc
+    #ifdef __riscv_xlen
+        #if __riscv_xlen == 64
+            lr.d t1, (t0)
+            sc.w t1, t3, (t5)
+         #endif
+    #else
+        ERROR: __riscv_xlen not defined
+    #endif
+
     addi t6, t6, 4      # increment offset
     slti t5, t6, 129    # offset <= 128
     bnez t5, 1b         # repeat until done
@@ -48,3 +59,78 @@
     sw t3, 0(t0)      # store word
     sc.w t5, t4, (t0) # succeeds
 
+    #ifdef __riscv_xlen
+        #if __riscv_xlen == 64
+            lr.w t1, (t0)
+            sd t3, 0(t0)      # store double
+            sc.w t5, t4, (t0) # succeeds
+        #endif
+    #else
+        ERROR: __riscv_xlen not defined
+    #endif
+
+# cp_custom_sc_after_load
+    # should not care about intervening loads
+
+    lr.w t1, (t0)
+    lb t3, 3(t0)      # load byte
+    sc.w t5, t4, (t0) # succeeds
+
+    lr.w t1, (t0)
+    lb t3, 128(t0)      # load byte
+    sc.w t5, t4, (t0) # succeeds
+
+    lr.w t1, (t0)
+    lbu t3, 2(t0)      # load byte unsigned
+    sc.w t5, t4, (t0) # succeeds
+
+    lr.w t1, (t0)
+    lbu t3, 128(t0)      # load byte unsigned
+    sc.w t5, t4, (t0) # succeeds
+
+    lr.w t1, (t0)
+    lh t3, 2(t0)      # load half
+    sc.w t5, t4, (t0) # succeeds
+
+    lr.w t1, (t0)
+    lh t3, 128(t0)      # load half
+    sc.w t5, t4, (t0) # succeeds
+
+    lr.w t1, (t0)
+    lhu t3, 0(t0)      # load half unsigned
+    sc.w t5, t4, (t0) # succeeds
+
+    lr.w t1, (t0)
+    lhu t3, 128(t0)      # load half unsigned
+    sc.w t5, t4, (t0) # succeeds
+
+    lr.w t1, (t0)
+    lw t3, 0(t0)      # load word
+    sc.w t5, t4, (t0) # succeeds
+
+    lr.w t1, (t0)
+    lw t3, 128(t0)      # load word
+    sc.w t5, t4, (t0) # succeeds
+
+    #ifdef __riscv_xlen
+        #if __riscv_xlen == 64
+            lr.w t1, (t0)
+            lwu t3, 0(t0)      # load word unsigned
+            sc.w t5, t4, (t0) # succeeds
+
+            lr.w t1, (t0)
+            lwu t3, 128(t0)      # load word unsigned
+            sc.w t5, t4, (t0) # succeeds
+
+            lr.w t1, (t0)
+            ld t3, 0(t0)      # load double
+            sc.w t5, t4, (t0) # succeeds
+
+            lr.w t1, (t0)
+            ld t3, 128(t0)      # load double
+            sc.w t5, t4, (t0) # succeeds
+
+        #endif
+    #else
+        ERROR: __riscv_xlen not defined
+    #endif