Fixed missing 6-bit immediate corners for Zca

README.md

@@ -30,8 +30,8 @@ This repo contains testplans, covergroups, and directed tests for the RVA22S64 p
 | Zalrsc |x |x | A extension: load reserved/store conditional |
 | Zba |x |x | B extension: address generation |
 | Zbb |x |x | B extension: basic bit manipulation |
-| Zbc |x |x | B extension: carry-free multiplication |
 | Zbs |x |x | B extension: single-bit operations |
+| Zbc |x |x | Carry-free multiplication |
 | Zca |x |x | Compressed instructions |
 | Zcb |x |x | Additional compressed instructions |
 | Zcf |x | | RV32 compressed single-precision fp |
@@ -45,7 +45,7 @@ This repo contains testplans, covergroups, and directed tests for the RVA22S64 p
 | Zicond |x |x | Conditional zero |
 | Zicbom |x |x | Cache block management, architecturally invisible |
 | Zicboz |x |x | Cach block zero |
-| Zicsr |x |x | CSR read/write/set/clear |
+| Zicsr |x |x | CSR read/write/set/clear instructions |
 | Zifencei |x |x | Instruction/data synchronization |
 | **Privileged** |
 | Zicsr |x |x | Excercise CSRs in each mode: M, S, U, F |
@@ -59,7 +59,7 @@ This repo contains testplans, covergroups, and directed tests for the RVA22S64 p
 | Fences |x |x | Tested in Zicsr |
 | Zihintpause |x |x | Tested in Zicsr |
 | Zicclsm |x |x | Misaligned access support is implicitly tested through accesses |
-| Ss1p12 |x |x | Implicit in Zicsr |
+| S{m/s}1p12 |x |x | Implicit in Zicsr |
 | Sstvala |x |x | stval implicity tested through exceptions |
 | Sscounterenw |x |x | Writable scounteren tested through Zicntr |
 | Ssu64xl | |x| RV64 sstatus.UXL tested through Zicsr |

bin/testgen.py

@@ -1265,9 +1265,12 @@ def make_rnum(test, xlen):
 def write_tests(coverpoints, test, xlen):
   global NaNBox_tests
   for coverpoint in coverpoints:
+    # produce a deterministic seed for repeatable random numbers 
+    # distinct for each instruction and coverpoint
+    seed(hash(test + coverpoint)) 
     if (coverpoint == "cp_asm_count"):
-      if (test == "c.nop"):   # Writing cp_asm_count for 'c.nop' only
-        f.write("\n# Testcase cp_asm_count\nc.nop\n")
+      if (test == "c.nop" or test == "fence"):   # Writing cp_asm_count for 'c.nop' only
+        f.write("\n# Testcase cp_asm_count\n"+test+"\n")
     elif (coverpoint == "cp_rd"):
       make_rd(test, xlen, range(32))
     elif(coverpoint == "cp_rd_nx0" or coverpoint == "cp_rd_nx2"):
@@ -1882,7 +1885,7 @@ def getExtensions():
                          0b1111111111111111111111111111111110000000000000000000000000000000]
 
 
-      corners_imm_12bits = [0, 1, 2, 1023, 1024, 2047, -2048, -2047, -2, -1]
+      corners_imm_12bits = [0, 1, 2, 3, 4, 8, 16, 32, 64, 128, 256, 512, 1023, 1024, 1795, 2047, -2048, -2047, -2, -1]
       corners_16bits = [0, 1, 2, 2**(15), 2**(15)+1,2**(15)-1, 2**(15)-2, 2**(16)-1, 2**(16)-2,
                     0b0101010101010101, 0b1010101010101010, 0b0101101110111100, 0b1101101110111100]
       corners_8bits = [0, 1, 2, 2**(7), 2**(7)+1,2**(7)-1, 2**(7)-2, 2**(8)-1, 2**(8)-2,

templates/cp_imm_corners_6bit.txt

@@ -0,0 +1,17 @@
+    cp_imm_corners_6bit : coverpoint unsigned'(ins.current.imm)  iff (ins.trap == 0 )  {
+        //Immediate value ones and zeros
+        bins b_0 = {0};
+        bins b_1 = {1};
+        bins b_2 = {2};
+        bins b_3 = {3};
+        bins b_4 = {4};
+        bins b_8 = {8};
+        bins b_16 = {16};
+        bins b_30 = {30};
+        bins b_31 = {31};
+        bins b_32 = {32};
+        bins b_33 = {33};
+        bins b_62 = {62};
+        bins b_63 = {63};
+    }
+    }

templates/sample_F.txt

@@ -0,0 +1,4 @@
+        "INSTR"     : begin 
+            ins = new(hart, issue, traceDataQ); 
+            ARCHCASE_INSTRNODOT_cg.sample(ins); 
+        end

testplans/I.csv

@@ -48,3 +48,4 @@ subw,R,,x,x,x,x,x,x,x,,x,x,x,x,x,x,x,,,,,,,,,,,,,,,rw,,,,,,,,,,,,,,,,,,,,,,
 sw,S,x,x,x,nx0,x,,,x,,,,,nx0,,,,,,x,,,,,,,,,,,,r,,,,,,,,,,,,,,,,,,,,,,
 xor,R,x,x,x,x,x,x,x,x,,x,x,x,x,x,x,x,,,,,,,,,,,,,,,rw,,,,,,,,,,,,,,,,,,,,,,
 xori,I,x,x,x,x,,x,x,,x,,x,,,x,,,,,x,,,,,,,,,,,,rw,,,,,,,,,,,,,,,,,,,,,,
+fence,F,x,x,x,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,