Skip to content

Commit

Permalink
Merge branch 'main' of https://github.com/openhwgroup/cvw-arch-verif …
Browse files Browse the repository at this point in the history 
…into dev
  • Loading branch information
@jordancarlin
jordancarlin committed Feb 23, 2025
2 parents 71d55e7 + 2c513b2 commit 654da72
Show file tree
Hide file tree
Showing 11 changed files with 221 additions and 92 deletions.
10 changes: 9 additions & 1 deletion Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,12 @@ SRCEXT := S
OBJEXT := elf
SIGEXT := elf.signature

# temporary for faster testing
#SRCDIR64 := $(LOCKSTEPDIR)/rv65
#SRCDIR32 := $(LOCKSTEPDIR)/rv32/I
#PRIVDIR := $(LOCKSTEPDIR)/bogus


# Dynamically find all source files
UNPRIV_SOURCES = $(shell find $(SRCDIR32) $(SRCDIR64) -type f -regex ".**\.$(SRCEXT)" | sort)
PRIVSOURCES = $(shell find $(PRIVDIR) -type f -regex ".**\.$(SRCEXT)" | sort)
Expand Down Expand Up @@ -110,8 +116,10 @@ EXTRADEPS = $(if $(findstring priv,$*),$(PRIV_HEADERS_EXPANDED) $(PRIVDIR$(BITW
# Compile tests
%.elf: $$(SOURCEFILE) $$(EXTRADEPS)
riscv64-unknown-elf-gcc -g -o $@ -march=rv$(BITWIDTH)g$(CMPR_FLAGS)_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zicond_zbkb_zbkx_zknd_zkne_zknh_zihintpause -mabi=$(MABI) -mcmodel=medany \
-nostartfiles -I$(TESTDIR) -I$(PRIVHEADERSDIR) -T$(TESTDIR)/link.ld $<
-nostartfiles -I$(TESTDIR) -I$(PRIVHEADERSDIR) -T$(TESTDIR)/link.ld -DLOCKSTEP=1 $<
# -nostartfiles -I$(TESTDIR) -I$(PRIVHEADERSDIR) -T$(TESTDIR)/link.ld -DSIGNATURE=1 $< # for signature generation
$(MAKE) [email protected] [email protected]
# $(MAKE) [email protected] [email protected] # uncomment for signature generation

%.elf.objdump: %.elf
riscv64-unknown-elf-objdump -S -D -M numeric -M no-aliases $< > $@
Expand Down
5 changes: 4 additions & 1 deletion bin/csrtests.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -38,6 +38,9 @@ def csrtests(pathname):
outfile = open(pathname, 'w')
sys.stdout = outfile
for i in range(4096):
if (i in list(range (0x800, 0x900)) + list(range(0x5C0, 0x600)) + list(range(0x6C0, 0x700)) + list(range(0x7B0-0x7C0)) + list(range(0x9C0, 0xA00)) +
list(range(0xBC0, 0xC00)) + list(range(0xCC0, 0xD00)) + list(range(0xDC0, 0xE00)) + list(range(0xEC0, 0xF00)) + list(range(0xFC0, 0x1000))):
continue # skip custom CSRs
reg1 = randint(1, 31)
reg2 = randint(1, 31)
reg3 = randint(1, 31)
Expand Down Expand Up @@ -65,7 +68,7 @@ def csrtests(pathname):
# generate repetitive assembly language tests

# writable registers to test with walking 1s and 0s
mregs = ["mstatus", "mcause", "misa", "medeleg", "mideleg", "mie", "mtvec", "mcounteren", "mscratch", "mepc", "mtval", "mip", "menvcfg", "mstatush", "mseccfg", "mseccfgh"]
mregs = ["mstatus", "mcause", "misa", "medeleg", "mideleg", "mie", "mtvec", "mcounteren", "mscratch", "mepc", "mtval", "mip", "menvcfg", "mstatush", "mseccfg", "mseccfgh", "menvcfgh", "0x312"] # 0x312 is medelegeh; RV64 compiler isn't accepting the name
sregs = ["sstatus", "scause", "sie", "stvec", "scounteren", "senvcfg", "sscratch", "sepc", "stval", "sip", "satp", "0x120"] # 0x120 is scountinhibit
uregs = ["fflags", "frm", "fcsr"]

Expand Down
13 changes: 7 additions & 6 deletions bin/illegalinstrtests.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -61,16 +61,16 @@ def gen(comment, template, len = 32, exclusion = []):
pathname = f"{ARCH_VERIF}/tests/lockstep/priv/headers/ExceptionInstr-Tests.h"
outfile = open(pathname, 'w')
sys.stdout = outfile
gen("Illegal op2", "RRRRRRRRRRRRRRRRRRRRRRRRR0001011")
#gen("Illegal op2", "RRRRRRRRRRRRRRRRRRRRRRRRR0001011") # custom-0
gen("Illegal op7", "RRRRRRRRRRRRRRRRRRRRRRRRR0011111")
gen("Illegal op10", "RRRRRRRRRRRRRRRRRRRRRRRRR0101011")
#gen("Illegal op10", "RRRRRRRRRRRRRRRRRRRRRRRRR0101011") # custom-1
gen("Illegal op15", "RRRRRRRRRRRRRRRRRRRRRRRRR0111111")
gen("Illegal op21", "RRRRRRRRRRRRRRRRRRRRRRRRR1010111")
gen("Illegal op22", "RRRRRRRRRRRRRRRRRRRRRRRRR1011011")
#gen("Illegal op22", "RRRRRRRRRRRRRRRRRRRRRRRRR1011011") # custom-2 / rv128
gen("Illegal op23", "RRRRRRRRRRRRRRRRRRRRRRRRR1011111")
gen("Illegal op26", "RRRRRRRRRRRRRRRRRRRRRRRRR1101011")
gen("Illegal op29", "RRRRRRRRRRRRRRRRRRRRRRRRR1110111")
gen("Illegal op30", "RRRRRRRRRRRRRRRRRRRRRRRRR1111011")
#gen("Illegal op30", "RRRRRRRRRRRRRRRRRRRRRRRRR1111011") # custom-3 / rv128
gen("Illegal op31", "RRRRRRRRRRRRRRRRRRRRRRRRR1111111")
gen("cp_load", "RRRRRRRRRRRRRRRRREEERRRRR0000011")
gen("cp_fload", "RRRRRRRRRRRRRRRRREEERRRRR0000111")
Expand Down Expand Up @@ -121,8 +121,9 @@ def gen(comment, template, len = 32, exclusion = []):
gen("cp_jalr2", "RRRRRRRRRRRRRRRRR100RRRRR1100111")
gen("cp_jalr3", "RRRRRRRRRRRRRRRRR110RRRRR1100111")
gen("cp_privileged_f3", "00000000000100000EEE000001110011")
gen("cp_privileged_000","EEEEEEEEEEEE00000000000001110011", 32,
["00X10000001000000000000001110011", # exclude mret and sret because there is no trap to return from
gen("cp_privileged_000","EEEEEEEEEEEE00000000000001110011", 32,
["1XXX11XXXXXX00000000000001110011", # exclude custom system instructions
"00X10000001000000000000001110011", # exclude mret and sret because there is no trap to return from
"00010000010100000000000001110011"]) # exclude wfi because it may not wake up
gen("cp_privileged_rd", "00000000000000000000EEEEE1110011")
gen("cp_privileged_rs2","000000000000EEEEE000000001110011")
Expand Down
66 changes: 45 additions & 21 deletions bin/testgen.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -121,6 +121,19 @@ def makeImm(imm, immlen, signed):
imm = imm - pow(2, immlen)
return str(imm)

def writeSIGUPD(rd):
[storeinstr, offsetInc] = getSigInfo(False)
tempReg = 0 # *** need to change this to get self-checking working with no conflicts on registers
l = f"RVTEST_SIGUPD(x{sigReg}, x{tempReg}, x{rd}, {sigOffset})\n"
#l = f"RVTEST_SIGUPD2({sigReg}, {rd})\n"
l = l + incrementSigOffset(offsetInc)
return l

def writeSIGUPD_F(rd):
# *** write this
return ""


def loadFloatReg(reg, val, xlen, flen): # *** eventually load from constant table instead
# Assumes that x2 is loaded with the base addres to avoid repeated `la` instructions
lines = "" # f"# Loading value {val} into f{reg}\n"
Expand Down Expand Up @@ -154,12 +167,17 @@ def loadFloatReg(reg, val, xlen, flen): # *** eventually load from constant tabl
def handleSignaturePointerConflict(lines, rs1, rs2, rd):
global sigReg # this function can modify the signature register
l = lines
if (not lockstep): # only needed for signature tests
oldSigReg = sigReg
while (sigReg == rs1 or sigReg == rs2 or sigReg == rd):
sigReg = (sigReg + 1) % 4 + 4
if (sigReg != oldSigReg):
l = lines + "mv x" + str(sigReg) + ", x" + str(oldSigReg) + " # switch signature pointer register to avoid conflict with test\n"
oldSigReg = sigReg
while (sigReg == rs1 or sigReg == rs2 or sigReg == rd):
sigReg = (sigReg + 1) % 4 + 4
if (sigReg != oldSigReg):
l = lines + "mv x" + str(sigReg) + ", x" + str(oldSigReg) + " # switch signature pointer register to avoid conflict with test\n"
# if (not lockstep): # only needed for signature tests
# oldSigReg = sigReg
# while (sigReg == rs1 or sigReg == rs2 or sigReg == rd):
# sigReg = (sigReg + 1) % 4 + 4
# if (sigReg != oldSigReg):
# l = lines + "mv x" + str(sigReg) + ", x" + str(oldSigReg) + " # switch signature pointer register to avoid conflict with test\n"
return l

# getSigInfo returns the store instruction and offset increment for the current test
Expand Down Expand Up @@ -197,24 +215,29 @@ def incrementSigOffset(amount):
return l
return ""


# writeTest appends the test to the lines.
# When doing signature generation, it also appends
# the signature logic
def writeTest(lines, rd, xlen, floatdest, testline):
l = lines + testline
if (not lockstep):
if (floatdest):
comment = "# FLOAT SIGNATURE\n"
else:
comment = "# INT SIGNATURE\n"
[storeinstr, offsetInc] = getSigInfo(floatdest)
rdPrefix = "f" if floatdest else "x"
l = l + f"{storeinstr} {rdPrefix}{rd}, {sigOffset}(x{sigReg}); nop; nop {comment}\n"
if (floatdest):
[intstoreinstr, dummy] = getSigInfo(False)
l = l + f"csrr x{rd}, fflags # read fflags\n"
l = l + f"{intstoreinstr} x{rd}, {sigOffset+offsetInc}(x{sigReg}); nop; nop # FFLAGS SIGNATURE\n"
l = l + incrementSigOffset(offsetInc*(2 if floatdest else 1))
if (floatdest):
l = l + writeSIGUPD_F(rd)
else:
l = l + writeSIGUPD(rd)
# if (not lockstep):
# if (floatdest):
# comment = "# FLOAT SIGNATURE\n"
# else:
# comment = "# INT SIGNATURE\n"
# [storeinstr, offsetInc] = getSigInfo(floatdest)
# rdPrefix = "f" if floatdest else "x"
# l = l + f"{storeinstr} {rdPrefix}{rd}, {sigOffset}(x{sigReg}); nop; nop {comment}\n"
# if (floatdest):
# [intstoreinstr, dummy] = getSigInfo(False)
# l = l + f"csrr x{rd}, fflags # read fflags\n"
# l = l + f"{intstoreinstr} x{rd}, {sigOffset+offsetInc}(x{sigReg}); nop; nop # FFLAGS SIGNATURE\n"
# l = l + incrementSigOffset(offsetInc*(2 if floatdest else 1))
return l

def writeJumpTest(lines, rd, rs1, xlen, jumpline):
Expand Down Expand Up @@ -2208,6 +2231,7 @@ def getExtensions():
maxreg = 31 # I uses registers x0-x31
#print(extensions)
for extension in extensions:
#for extension in ["I"]: # temporary for faster run
coverdefdir = f"{ARCH_VERIF}/fcov/unpriv"
coverfiles = [extension]
coverpoints = getcovergroups(coverdefdir, coverfiles, xlen)
Expand All @@ -2233,9 +2257,9 @@ def getExtensions():
formatstrFP = "0x{:0" + formatstrlenFP + "x}" # format as flen-bit hexadecimal number
corners = [0, 1, 2, 2**(xlen-1), 2**(xlen-1)+1, 2**(xlen-1)-1, 2**(xlen-1)-2, 2**xlen-1, 2**xlen-2]
if (xlen == 32):
corners = corners + [0b01011011101111001000100001110111, 0b10101010101010101010101010101010, 0b01010101010101010101010101010101]
corners = corners + [0b01011011101111001000100001110010, 0b10101010101010101010101010101010, 0b01010101010101010101010101010101]
else:
corners = corners + [0b0101101110111100100010000111011101100011101011101000011011110111, # random
corners = corners + [0b0101101110111100100010000111011101100011101011101000011011110010, # random
0b1010101010101010101010101010101010101010101010101010101010101010, # walking odd
0b0101010101010101010101010101010101010101010101010101010101010101, # walking even
0b0000000000000000000000000000000011111111111111111111111111111111, # Wmax
Expand Down
23 changes: 12 additions & 11 deletions fcov/priv/ExceptionsM_coverage.svh
View file
Original file line number Diff line number Diff line change
Expand Up @@ -155,17 +155,17 @@ covergroup ExceptionsM_instr_cg with function sample(ins_t ins);
option.per_instance = 0;

cp_illegal : coverpoint ins.current.insn { // illegal in RVA22S64; will trap if not in an implemented extension
wildcard bins op2 = {32'b?????????????????????????_0001011}; // unused ops
wildcard bins op7 = {32'b?????????????????????????_0011111}; // unused ops
wildcard bins op10 = {32'b?????????????????????????_0101011}; // unused ops
wildcard bins op15 = {32'b?????????????????????????_0111111}; // unused ops
wildcard bins op21 = {32'b?????????????????????????_1010111}; // unused ops
wildcard bins op22 = {32'b?????????????????????????_1011011}; // unused ops
wildcard bins op23 = {32'b?????????????????????????_1011111}; // unused ops
wildcard bins op26 = {32'b?????????????????????????_1101011}; // unused ops
wildcard bins op29 = {32'b?????????????????????????_1110111}; // unused ops
wildcard bins op30 = {32'b?????????????????????????_1111011}; // unused ops
wildcard bins op31 = {32'b?????????????????????????_1111111}; // unused ops
// wildcard bins op2 = {32'b?????????????????????????_0001011}; // unused ops custom-0
wildcard bins op7 = {32'b?????????????????????????_0011111}; // unused ops, reserved for 48-bit
// wildcard bins op10 = {32'b?????????????????????????_0101011}; // unused ops custom-1
wildcard bins op15 = {32'b?????????????????????????_0111111}; // unused ops, reserved for 64-bit
wildcard bins op21 = {32'b?????????????????????????_1010111}; // vector ops
// wildcard bins op22 = {32'b?????????????????????????_1011011}; // unused ops custom-2/rv128
wildcard bins op23 = {32'b?????????????????????????_1011111}; // unused ops, reserved for 48-bit
wildcard bins op26 = {32'b?????????????????????????_1101011}; // reserved
wildcard bins op29 = {32'b?????????????????????????_1110111}; // VE vector ops
// wildcard bins op30 = {32'b?????????????????????????_1111011}; // unused ops custom-2/rv128
wildcard bins op31 = {32'b?????????????????????????_1111111}; // unused ops, reserved for 80+ bit
}
// Loads op = 0000011
cp_load : coverpoint ins.current.insn[14:12] iff (ins.current.insn[6:0] == 7'b0000011) {
Expand Down Expand Up @@ -295,6 +295,7 @@ covergroup ExceptionsM_instr_cg with function sample(ins_t ins);
// focus on funct3 = 0; others are covered by csr tests
cp_privileged_000 : coverpoint ins.current.insn[31:20] iff (ins.current.insn[6:0] == 7'b1110011 & ins.current.insn[14:12] == 3'b000 & ins.current.insn[19:15] == 5'b00000 & ins.current.insn[11:7] == 5'b00000) {
// Exhaustive test of 2^12 encodings, only a few are legal
wildcard ignore_bins custom = {12'b1???11??????}; // custom System instructions don't need checking
}
// if funct3 = 0, rd must be 0
cp_privileged_rd : coverpoint ins.current.insn[11:7] iff (ins.current.insn[6:0] == 7'b1110011 & ins.current.insn[14:12] == 3'b000) {
Expand Down
32 changes: 29 additions & 3 deletions fcov/priv/ZicsrM_coverage.svh
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,33 @@ covergroup ZicsrM_mcsr_cg with function sample(ins_t ins);
wildcard bins csrrw = {32'b????????????_?????_001_?????_1110011};
}
csr: coverpoint ins.current.insn[31:20] {
bins all[] = {[0:$]};
bins user_std0[] = {[12'h000:12'h0FF]};
bins super_std0[] = {[12'h100:12'h1FF]};
bins hyper_std0[] = {[12'h200:12'h2FF]};
bins mach_std0[] = {[12'h300:12'h3FF]};
bins user_std1[] = {[12'h400:12'h4FF]};
bins super_std1[] = {[12'h500:12'h5BF]};
ignore_bins super_custom1[] = {[12'h5C0:12'h5FF]};
bins hyper_std1[] = {[12'h600:12'h6BF]};
ignore_bins hyper_custom1[] = {[12'h6C0:12'h6FF]};
bins mach_std1[] = {[12'h700:12'h7AF]};
ignore_bins mach_debug[] = {[12'h7B0:12'h7BF]}; // toggling debug registers could do weird stuff
ignore_bins mach_custom1[] = {[12'h7C0:12'h7FF]};
ignore_bins user_custom2[] = {[12'h800:12'h8FF]};
bins super_std2[] = {[12'h900:12'h9BF]};
ignore_bins super_custom22[] = {[12'h9C0:12'h9FF]};
bins hyper_std2[] = {[12'hA00:12'hABF]};
ignore_bins hyper_custom22[] = {[12'hAC0:12'hAFF]};
bins mach_std2[] = {[12'hB00:12'hBBF]};
ignore_bins mach_custom2[] = {[12'hBC0:12'hBFF]};
bins user_std3[] = {[12'hC00:12'hCBF]};
ignore_bins user_custom3[] = {[12'hCC0:12'hCFF]};
bins super_std3[] = {[12'hD00:12'hDBF]};
ignore_bins super_custom3[] = {[12'hDC0:12'hDFF]};
bins hyper_std3[] = {[12'hE00:12'hEBF]};
ignore_bins hyper_custom3[] = {[12'hEC0:12'hEFF]};
bins mach_std3[] = {[12'hF00:12'hFBF]};
ignore_bins mach_custom3[] = {[12'hFC0:12'hFFF]};
}
priv_mode_m: coverpoint ins.current.mode {
bins M_mode = {2'b11};
Expand Down Expand Up @@ -151,7 +177,7 @@ covergroup ZicsrM_mcsr_cg with function sample(ins_t ins);
}
`endif

csrname : coverpoint ins.current.insn[31:20] {
mcsrname : coverpoint ins.current.insn[31:20] {
bins mstatus = {12'h300};
bins misa = {12'h301};
bins medeleg = {12'h302};
Expand Down Expand Up @@ -182,7 +208,7 @@ covergroup ZicsrM_mcsr_cg with function sample(ins_t ins);
cp_csrr: cross csrr, csr, priv_mode_m, nonzerord; // CSR read of all 4096 registers
cp_csrw_corners: cross csrrw, csr, priv_mode_m, rs1_corners; // CSR write of all 0s / all 1s to all 4096 registers
cp_csrcs: cross csrop, csr, priv_mode_m, rs1_ones; // CSR clear and set of all bits of all registers
cp_mcsrwalk : cross csrname, csrop, priv_mode_m, walking_ones;
cp_mcsrwalk : cross mcsrname, csrop, priv_mode_m, walking_ones;
endgroup

covergroup ZicsrM_mcause_cg with function sample(ins_t ins);
Expand Down
2 changes: 1 addition & 1 deletion templates/coverage/cp_rs1_corners.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,6 @@
bins onesm1 = {64'b1111111111111111111111111111111111111111111111111111111111111110};
bins walkeodd = {64'b1010101010101010101010101010101010101010101010101010101010101010};
bins walkeven = {64'b0101010101010101010101010101010101010101010101010101010101010101};
bins random = {64'b0101101110111100100010000111011101100011101011101000011011110111};
wildcard bins random = {64'b01???????????????????????????????????????????????????????????010};
`endif
}
4 changes: 2 additions & 2 deletions templates/coverage/cp_rs2_corners.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@
bins onesm1 = {32'b11111111111111111111111111111110};
bins walkeodd = {32'b10101010101010101010101010101010};
bins walkeven = {32'b01010101010101010101010101010101};
bins random = {32'b01011011101111001000100001110111};
wildcard bins random = {32'b01???????????????????????????010};
`else
bins zero = {0};
bins one = {64'b0000000000000000000000000000000000000000000000000000000000000001};
Expand All @@ -28,6 +28,6 @@
bins onesm1 = {64'b1111111111111111111111111111111111111111111111111111111111111110};
bins walkeodd = {64'b1010101010101010101010101010101010101010101010101010101010101010};
bins walkeven = {64'b0101010101010101010101010101010101010101010101010101010101010101};
bins random = {64'b0101101110111100100010000111011101100011101011101000011011110111};
wildcard bins random = {64'b01???????????????????????????????????????????????????????????010};
`endif
}
Loading

0 comments on commit 654da72

Please sign in to comment.