feat(riscv): better codegen for conditionals#974
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VeIR Benchmarks
Details
| Benchmark suite | Current: 369700b | Previous: fc5ee5b | Ratio |
|---|---|---|---|
add-fold-worklist/create |
2243000 ns (± 101935) |
2261000 ns (± 44489) |
0.99 |
add-fold-worklist/rewrite |
4057000 ns (± 40917) |
4041000 ns (± 68252) |
1.00 |
add-fold-worklist-local/create |
2137000 ns (± 104507) |
2183000 ns (± 30573) |
0.98 |
add-fold-worklist-local/rewrite |
3321000 ns (± 93302) |
3324000 ns (± 56690) |
1.00 |
add-zero-worklist/create |
2178000 ns (± 104059) |
2291000 ns (± 84009) |
0.95 |
add-zero-worklist/rewrite |
2532000 ns (± 36753) |
2630000 ns (± 59551) |
0.96 |
add-zero-reuse-worklist/create |
1810000 ns (± 89704) |
1845000 ns (± 79748) |
0.98 |
add-zero-reuse-worklist/rewrite |
2096000 ns (± 19972) |
2149000 ns (± 68678) |
0.98 |
mul-two-worklist/create |
2218000 ns (± 57201) |
2213000 ns (± 59036) |
1.00 |
mul-two-worklist/rewrite |
5501000 ns (± 110592) |
5752000 ns (± 188041) |
0.96 |
add-fold-forwards/create |
2232000 ns (± 64450) |
2198000 ns (± 97548) |
1.02 |
add-fold-forwards/rewrite |
2991000 ns (± 43587) |
3057000 ns (± 48925) |
0.98 |
add-zero-forwards/create |
2186000 ns (± 66375) |
2177000 ns (± 65592) |
1.00 |
add-zero-forwards/rewrite |
1910000 ns (± 10733) |
1976000 ns (± 49558) |
0.97 |
add-zero-reuse-forwards/create |
1855000 ns (± 194116) |
1813000 ns (± 66624) |
1.02 |
add-zero-reuse-forwards/rewrite |
1543500 ns (± 101401) |
1535000 ns (± 71922) |
1.01 |
mul-two-forwards/create |
2185000 ns (± 65590) |
2249000 ns (± 59277) |
0.97 |
mul-two-forwards/rewrite |
3582000 ns (± 34392) |
3718000 ns (± 43701) |
0.96 |
add-zero-reuse-first/create |
1817000 ns (± 83503) |
1848500 ns (± 77966) |
0.98 |
add-zero-reuse-first/rewrite |
8000 ns (± 3277) |
8000 ns (± 1982) |
1 |
add-zero-lots-of-reuse-first/create |
1880000 ns (± 47925) |
1872000 ns (± 26678) |
1.00 |
add-zero-lots-of-reuse-first/rewrite |
764000 ns (± 19282) |
837000 ns (± 34120) |
0.91 |
This comment was automatically generated by workflow using github-action-benchmark.
…mizing # Conflicts: # Test/Passes/InstructionSelection/RISCV64/fastntt.mlir
tobiasgrosser
approved these changes
Jul 4, 2026
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this PR does a few things:
li 0in it, and switch this over to a use of the RISC-V zero registericmpforms. notably, f1-f4 inTest/Passes/InstructionSelection/RISCV64/icmp_imm.mlircodegen then same usingveirasllc!these changes make our lowering of
fastnttseveral instructions smaller!