This repository is full of components that are used in a 5-stage pipelined processor - with a 32 bit MIPs-like ISA.
All the components are written in structural Verilog, except for interior FSM modules.
I hope this repository serves as a reference resource for other students learning about basic processor design in their engineering classes.
Github seems to be having trouble with distinguishing between Verilog files and Coq files, since they both use the .v extension. I can assure you that all files in this repository are Verilog files.