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rugeGerritsenadamkondraciuk
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[nrf fromlist] soc: nordic: nrf54h: s2ram: Use ARM FPU save/restore funcs
This reduced the amount of duplicate code and unifies the code with other platforms. With this change the caller and callee status registers are stored separately. Also, a different set of status registers are stored: - FPSCR instead of FPDSCR. FPDSCR contains the default values to be assigned to FPSCR when a new floating-point context is created. It therefore seems more correct to store the FPSCR. - FPCCR and FPCAR are no longer stored. FPU retention was originally added in: 8a5365c. Upstream PR #: 97073 Signed-off-by: Rubin Gerritsen <[email protected]>
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soc/nordic/nrf54h/pm_s2ram.c

Lines changed: 4 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
#include <zephyr/arch/cpu.h>
77
#include <zephyr/arch/arm/mpu/arm_mpu.h>
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#include <zephyr/arch/arm/cortex_m/scb.h>
9+
#include <zephyr/arch/arm/cortex_m/fpu.h>
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#include <zephyr/arch/common/pm_s2ram.h>
1011
#include <zephyr/linker/sections.h>
1112
#include <zephyr/sys/util.h>
@@ -19,33 +20,21 @@
1920

2021
/* Coprocessor Power Control Register Definitions */
2122

22-
#define SCnSCB_CPPWR_SU10_Pos 20U /*!< CPPWR: SU10 Position */
23-
#define SCnSCB_CPPWR_SU10_Msk (1UL << SCnSCB_CPPWR_SU10_Pos) /*!< CPPWR: SU10 Mask */
24-
2523
typedef struct {
2624
/* NVIC components stored into RAM. */
2725
uint32_t ISER[NVIC_MEMBER_SIZE(ISER)];
2826
uint32_t ISPR[NVIC_MEMBER_SIZE(ISPR)];
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uint8_t IPR[NVIC_MEMBER_SIZE(IPR)];
3028
} _nvic_context_t;
3129

32-
#if defined(CONFIG_FPU) && !defined(CONFIG_FPU_SHARING)
33-
typedef struct {
34-
uint32_t FPCCR;
35-
uint32_t FPCAR;
36-
uint32_t FPDSCR;
37-
uint32_t S[32];
38-
} _fpu_context_t;
39-
#endif
40-
4130
struct backup {
4231
_nvic_context_t nvic_context;
4332
#if defined(CONFIG_ARM_MPU)
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struct z_mpu_context_retained mpu_context;
4534
#endif
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struct scb_context scb_context;
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#if defined(CONFIG_FPU) && !defined(CONFIG_FPU_SHARING)
48-
_fpu_context_t fpu_context;
37+
struct fpu_ctx_full fpu_context;
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#endif
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};
5140

@@ -81,26 +70,6 @@ static void fpu_power_up(void)
8170
__DSB();
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__ISB();
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}
84-
85-
#if !defined(CONFIG_FPU_SHARING)
86-
static void fpu_save(_fpu_context_t *backup)
87-
{
88-
backup->FPCCR = FPU->FPCCR;
89-
backup->FPCAR = FPU->FPCAR;
90-
backup->FPDSCR = FPU->FPDSCR;
91-
92-
__asm__ volatile("vstmia %0, {s0-s31}\n" : : "r"(backup->S) : "memory");
93-
}
94-
95-
static void fpu_restore(_fpu_context_t *backup)
96-
{
97-
FPU->FPCCR = backup->FPCCR;
98-
FPU->FPCAR = backup->FPCAR;
99-
FPU->FPDSCR = backup->FPDSCR;
100-
101-
__asm__ volatile("vldmia %0, {s0-s31}\n" : : "r"(backup->S) : "memory");
102-
}
103-
#endif /* !defined(CONFIG_FPU_SHARING) */
10473
#endif /* defined(CONFIG_FPU) */
10574

10675
#if DT_NODE_EXISTS(DT_NODELABEL(mcuboot_s2ram)) &&\
@@ -124,7 +93,7 @@ int soc_s2ram_suspend(pm_s2ram_system_off_fn_t system_off)
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z_arm_save_scb_context(&backup_data.scb_context);
12594
#if defined(CONFIG_FPU)
12695
#if !defined(CONFIG_FPU_SHARING)
127-
fpu_save(&backup_data.fpu_context);
96+
z_arm_save_fp_context(&backup_data.fpu_context);
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#endif
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fpu_power_down();
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#endif
@@ -139,7 +108,7 @@ int soc_s2ram_suspend(pm_s2ram_system_off_fn_t system_off)
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fpu_power_up();
140109
#if !defined(CONFIG_FPU_SHARING)
141110
/* Also the FPU content might be lost. */
142-
fpu_restore(&backup_data.fpu_context);
111+
z_arm_restore_fp_context(&backup_data.fpu_context);
143112
#endif
144113
#endif
145114
if (ret < 0) {

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