[nrf fromlist] soc: nordic: nrf54h: s2ram: Use ARM SCB save/restore funcs

This reduced the amount of duplicate code and unifies the code
with other platforms.

With this change fewer registers are stored and restored.
See also comment in scb.h for scb_context stating that
only essential registers are stored and restored.

No longer stored:
- ICSR
- SCR
- CFSR
- HFSR
- DFSR
- MMFAR
- BFAR
- AFSR

No longer used:
- SHPR[3..12]. This backup register was declared in the wrong way.
  In core_cm33.h and core_cm4.h this is declared as an array of
  12 uint8_t's. That is 3 uint32_t's.

Orignal SCB retention was added in
2055f7d.

Upstream PR #: 97073

Signed-off-by: Rubin Gerritsen <[email protected]>

Author: rugeGerritsen

soc/nordic/nrf54h/pm_s2ram.c

@@ -5,6 +5,7 @@
 
 #include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/mpu/arm_mpu.h>
+#include <zephyr/arch/arm/cortex_m/scb.h>
 #include <zephyr/arch/common/pm_s2ram.h>
 #include <zephyr/linker/sections.h>
 #include <zephyr/sys/util.h>
@@ -17,8 +18,6 @@
 #define NVIC_MEMBER_SIZE(member) ARRAY_SIZE(((NVIC_Type *)0)->member)
 
 /* Coprocessor Power Control Register Definitions */
-#define SCnSCB_CPPWR_SU11_Pos 22U                            /*!< CPPWR: SU11 Position */
-#define SCnSCB_CPPWR_SU11_Msk (1UL << SCnSCB_CPPWR_SU11_Pos) /*!< CPPWR: SU11 Mask */
 
 #define SCnSCB_CPPWR_SU10_Pos 20U                            /*!< CPPWR: SU10 Position */
 #define SCnSCB_CPPWR_SU10_Msk (1UL << SCnSCB_CPPWR_SU10_Pos) /*!< CPPWR: SU10 Mask */
@@ -30,23 +29,6 @@ typedef struct {
 	uint8_t IPR[NVIC_MEMBER_SIZE(IPR)];
 } _nvic_context_t;
 
-typedef struct {
-	uint32_t ICSR;
-	uint32_t VTOR;
-	uint32_t AIRCR;
-	uint32_t SCR;
-	uint32_t CCR;
-	uint32_t SHPR[12U];
-	uint32_t SHCSR;
-	uint32_t CFSR;
-	uint32_t HFSR;
-	uint32_t DFSR;
-	uint32_t MMFAR;
-	uint32_t BFAR;
-	uint32_t AFSR;
-	uint32_t CPACR;
-} _scb_context_t;
-
 #if defined(CONFIG_FPU) && !defined(CONFIG_FPU_SHARING)
 typedef struct {
 	uint32_t FPCCR;
@@ -61,7 +43,7 @@ struct backup {
 #if defined(CONFIG_ARM_MPU)
 	struct z_mpu_context_retained mpu_context;
 #endif
-	_scb_context_t scb_context;
+	struct scb_context scb_context;
 #if defined(CONFIG_FPU) && !defined(CONFIG_FPU_SHARING)
 	_fpu_context_t fpu_context;
 #endif
@@ -83,42 +65,6 @@ static void nvic_restore(_nvic_context_t *backup)
 	memcpy((uint32_t *)NVIC->IPR, backup->IPR, sizeof(NVIC->IPR));
 }
 
-static void scb_save(_scb_context_t *backup)
-{
-	backup->ICSR = SCB->ICSR;
-	backup->VTOR = SCB->VTOR;
-	backup->AIRCR = SCB->AIRCR;
-	backup->SCR = SCB->SCR;
-	backup->CCR = SCB->CCR;
-	memcpy(backup->SHPR, (uint32_t *)SCB->SHPR, sizeof(SCB->SHPR));
-	backup->SHCSR = SCB->SHCSR;
-	backup->CFSR = SCB->CFSR;
-	backup->HFSR = SCB->HFSR;
-	backup->DFSR = SCB->DFSR;
-	backup->MMFAR = SCB->MMFAR;
-	backup->BFAR = SCB->BFAR;
-	backup->AFSR = SCB->AFSR;
-	backup->CPACR = SCB->CPACR;
-}
-
-static void scb_restore(_scb_context_t *backup)
-{
-	SCB->ICSR = backup->ICSR;
-	SCB->VTOR = backup->VTOR;
-	SCB->AIRCR = backup->AIRCR;
-	SCB->SCR = backup->SCR;
-	SCB->CCR = backup->CCR;
-	memcpy((uint32_t *)SCB->SHPR, backup->SHPR, sizeof(SCB->SHPR));
-	SCB->SHCSR = backup->SHCSR;
-	SCB->CFSR = backup->CFSR;
-	SCB->HFSR = backup->HFSR;
-	SCB->DFSR = backup->DFSR;
-	SCB->MMFAR = backup->MMFAR;
-	SCB->BFAR = backup->BFAR;
-	SCB->AFSR = backup->AFSR;
-	SCB->CPACR = backup->CPACR;
-}
-
 #if defined(CONFIG_FPU)
 static void fpu_power_down(void)
 {
@@ -175,7 +121,7 @@ int soc_s2ram_suspend(pm_s2ram_system_off_fn_t system_off)
 	int ret;
 
 	SET_MCUBOOT_RESUME_MAGIC();
-	scb_save(&backup_data.scb_context);
+	z_arm_save_scb_context(&backup_data.scb_context);
 #if defined(CONFIG_FPU)
 #if !defined(CONFIG_FPU_SHARING)
 	fpu_save(&backup_data.fpu_context);
@@ -204,7 +150,7 @@ int soc_s2ram_suspend(pm_s2ram_system_off_fn_t system_off)
 	z_arm_restore_mpu_context(&backup_data.mpu_context);
 #endif
 	nvic_restore(&backup_data.nvic_context);
-	scb_restore(&backup_data.scb_context);
+	z_arm_restore_scb_context(&backup_data.scb_context);
 
 	return ret;
 }