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More complete implementation of the semantics #14

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More complete implementation of the semantics #14

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pleroy
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@pleroy pleroy commented Dec 15, 2024

  1. Instruction normalization has access to both the ISA and the arch model.
  2. Fix instruction normalization for Intel, notably by append a GAS suffix based on the operand data type and by implementing default handling of instruction that are not found in the database.
  3. Move more code to the x86 base parser.
  4. Add support for negative displacements to the Intel parser.
  5. Change the test kernels to more closely resemble those for AT&T.
  6. Add two semantic tests for Intel.

eggrobin
eggrobin reviewed Dec 15, 2024
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osaca/parser/parser_x86intel.py
sources = instruction_form.operands[1:]
destination = instruction_form.operands[0]
sources.append(destination)
instruction_form.operands = sources
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Maybe instruction_form.operands = sources + [destination] would be clearer?

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@eggrobin eggrobin eggrobin approved these changes

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