[CUDA] columnwise quantize with tma - #3157
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| #if (CUDART_VERSION >= 12080) && (__CUDA_ARCH__ >= 1000) && \ | ||
| defined(__CUDA_ARCH_SPECIFIC__) | ||
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| __device__ __forceinline__ void mbarrier_init(uint64_t* mbar, uint32_t count) { |
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Should we use the cuda::ptx APIs like cuda::ptx::mbarrier_init API instead? They don't have good documentation and you would have to search https://github.com/NVIDIA/cccl to find out API names though.
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Thanks, great question. My intention with raw PTX was to make sure I understand exactly what each instruction does. I felt that when wrapped in ccc up the details are hidden bit, so writing them in a raw ptx makes them explicit. I agree on docs point. That being said if you have a strong preference, I am happy to substitute it with cccl functions :)
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@nastya236 is there any reason not to merge this? Will do a quick pass but I think it should be good to go, isn't it? |
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The reason we have not merged it is that i was too slow to respond to Cheng's comment. I think it is mergable, thank you! |
Columnwise quantization with tma (mxfp8), bfloat16:
This PR:
get_swizzle_launch_argsintocu::namespace for consistencyThe diff seems bigger than it is: since
fp_quantize.cualready contains all the logic for block quantization, I decided to split it intofp_quantize.cuandfp_quantize.cuhto separate dispatch from kernel implementation.TODO:
nvfp4requires a separate columnwise kernel due to TMA tile size constraints. In the proposed kernel each thread processing a tile of size (N, M) and store a transposed result. M is equal togroup_size-- 32 bytes formcfp8, but only 8 bytes fornvfp4. Since TMA requires the innermost tile dimension to be at least 128 bits (16 bytes), fornvfp4kernel would need to load a larger tile and iterate over multiple groups.