MIPS pipline

A classic 5-stage pipeline MIPS 32-bit processor.

five stages of a microprocessor: instruction fetch (IF), instruction decode (ID), execution(EX), memory access and write (MEM) e write back (WB).

#name of wire and guideline

#states

support most of MIPS instruction and solve every hazard with stall.(Data Hazards and Control Hazards) Verilog code.

Developed during the winter 2019 Computer Architecture Laboratory course at the University of Ferdowsi Mashhad.

Modular design

code start from mypip

other modular named same to original model

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
screenshots		screenshots
ALU.v		ALU.v
ALUcontrol.v		ALUcontrol.v
Controlstall.v		Controlstall.v
DM.v		DM.v
EXMEM.v		EXMEM.v
IDEX.v		IDEX.v
InstMem.v		InstMem.v
MEMWB.v		MEMWB.v
MUX.v		MUX.v
PC.v		PC.v
README.md		README.md
RegFile.v		RegFile.v
adder32bit.v		adder32bit.v
concatforJump.v		concatforJump.v
controlunit.v		controlunit.v
mypip.v		mypip.v
shiftleft.v		shiftleft.v
signExt.v		signExt.v
stall.v		stall.v
tb.v		tb.v