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1 | 1 | # Project log
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2 | 2 |
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| 3 | +## Instruction support |
| 4 | + |
| 5 | +### Data Transfer Instructions |
| 6 | + |
| 7 | +- [ ] LUI: Load Upper Immediate |
| 8 | +- [ ] AUIPC: Add Upper Immediate to PC |
| 9 | +- [ ] ADDI: Add Immediate |
| 10 | +- [ ] SLTI: Set Less Than Immediate (Signed) |
| 11 | +- [ ] SLTIU: Set Less Than Immediate Unsigned |
| 12 | +- [ ] XORI: Bitwise XOR Immediate |
| 13 | +- [ ] ORI: Bitwise OR Immediate |
| 14 | +- [ ] ANDI: Bitwise AND Immediate |
| 15 | + |
| 16 | +### Register-Register Arithmetic Instructions |
| 17 | + |
| 18 | +- [ ] ADD: Add |
| 19 | +- [ ] SUB: Subtract |
| 20 | +- [ ] SLL: Shift Left Logical |
| 21 | +- [ ] SLT: Set Less Than (Signed) |
| 22 | +- [ ] SLTU: Set Less Than Unsigned |
| 23 | +- [ ] XOR: Bitwise XOR |
| 24 | +- [ ] SRL: Shift Right Logical |
| 25 | +- [ ] SRA: Shift Right Arithmetic |
| 26 | +- [ ] OR: Bitwise OR |
| 27 | +- [ ] AND: Bitwise AND |
| 28 | + |
| 29 | +### Memory Access Instructions |
| 30 | + |
| 31 | +- [ ] LB: Load Byte (Signed) |
| 32 | +- [ ] LH: Load Halfword (Signed) |
| 33 | +- [ ] LW: Load Word |
| 34 | +- [ ] LBU: Load Byte Unsigned |
| 35 | +- [ ] LHU: Load Halfword Unsigned |
| 36 | +- [ ] SB: Store Byte |
| 37 | +- [ ] SH: Store Halfword |
| 38 | +- [ ] SW: Store Word |
| 39 | + |
| 40 | +### Control Transfer Instructions |
| 41 | + |
| 42 | +- [ ] BEQ: Branch Equal |
| 43 | +- [ ] BNE: Branch Not Equal |
| 44 | +- [ ] BLT: Branch Less Than (Signed) |
| 45 | +- [ ] BGE: Branch Greater Than or Equal (Signed) |
| 46 | +- [ ] BLTU: Branch Less Than Unsigned |
| 47 | +- [ ] BGEU: Branch Greater Than or Equal Unsigned |
| 48 | +- [ ] JAL: Jump and Link |
| 49 | +- [ ] JALR: Jump and Link Register |
| 50 | + |
| 51 | +### System Instructions |
| 52 | + |
| 53 | +- [ ] ECALL: Environment Call |
| 54 | +- [ ] EBREAK: Environment Breakpoint |
| 55 | + |
3 | 56 | ## TODO
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4 | 57 |
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5 | 58 | - turn instrmem and regfile into BRAM, memory maybe SPRAM
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