Add codespell and fix spelling mistakes

Author: matiasilva

README.md

@@ -14,7 +14,7 @@ All Makefiles rely on the `$ROOT` variable being set, which you can get by
 sourcing the appropriately named `sourceme` file.
 
 Full information on running simulations and the project setup are available on
-the [project page](https://matiasilva.github.io/riscv-soc/tools.html)
+the [project page](https://matiasilva.github.io/riscv-soc/tools.html).
 
 ## Author
 

docs/pyproject.toml

@@ -5,9 +5,10 @@ description = "A minimal RISC-V SoC containing an RV32I-compliant core, a UART a
 readme = "README.md"
 requires-python = ">=3.13"
 dependencies = [
-    "furo>=2024.8.6",
-    "myst-parser>=4.0.0",
-    "sphinx-last-updated-by-git>=0.3.8",
-    "sphinx>=8.1.3",
-    "sphinx-autobuild>=2024.10.3",
+  "furo>=2024.8.6",
+  "myst-parser>=4.0.0",
+  "sphinx-last-updated-by-git>=0.3.8",
+  "sphinx>=8.1.3",
+  "sphinx-autobuild>=2024.10.3",
+  "codespell>=2.3.0",
 ]

docs/src/motivation.md

@@ -46,7 +46,7 @@ My main goals with the project were to:
 1. develop a deeper understanding of digital design, verification and compilers
 1. to understand the hardware stack from the bottom up: gates to kernel to
    userland software
-1. learn about RISC-V, computer architeture and ISAs
+1. learn about RISC-V, computer architecture and ISAs
 
 Along the way, I greatly refined my command of Neovim for documentation writing
 and code, which I'd been trying to pick up for forever.

docs/src/tools.md

@@ -28,6 +28,17 @@ needed. While I was wrapping my head around this, I found
 explaining each step of the design flow and how that interlinks with these open
 source tools.
 
+## Codespell
+
+A painless way to prevent any spelling mistakes in source code and/or
+documentation is using
+[codespell](https://github.com/codespell-project/codespell/). This is a quick
+command to check spelling:
+
+```bash
+uv run codespell $ROOT/hdl $ROOT/docs/src
+```
+
 ## Extra steps
 
 ### Mounting the iCESugar board

docs/uv.lock

@@ -1,6 +1,5 @@
 /*
 generates the necessary control signals for muxes
-
 [alusrc] select sign-extended immediate OR rs2 field of instruction
 [reg_wr_en] enable writeback to regfile
 [is_mem_to_reg] select whether ALU result or memory read is written to regfile

hdl/control.v

@@ -0,0 +1,2 @@
+#!/usr/bin/env bash
+export ROOT="$(dirname "$(realpath "$0")")"