Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

bus/rs232: Add the Cricket external sound box for the Apple IIc. #13343

Open
wants to merge 4 commits into
base: master
Choose a base branch
from

Conversation

robjustice
Copy link
Contributor

Emulation of the Street Electronics the Cricket for the Apple IIc. Disks and rom dump is pending to be added to the A2DP. Can be grabbed from here as well: https://archive.org/download/cricket-6801-03-801-00/Cricket_6801_03-801-00.bin

@rb6502
Copy link
Contributor

rb6502 commented Feb 9, 2025

You'll need to change the short device name to fix "mame -validate" since "cricket" is already taken. Maybe "secricket" or something similar.

I don't know how the clock works (looks like it's stored in the 6801's internal RAM?) but it might be interesting to also inherit device_rtc_interface so it can be auto-set to the host machine's time/date on startup. I won't hold up a merge for that though.

@robjustice
Copy link
Contributor Author

I have updated that, thanks.

That would be nice to set the clock. I'm assuming its stored in 6801's Internal ram as well. Must be some sort of flag generated or set to say its been updated, would just need to work that part of the puzzle out.

Comment on lines 225 to 233
u8 cricket_device::p4_r()
{
return m_data;
}

void cricket_device::p4_w(u8 data)
{
m_data = data;
}
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

You seem to be using m_data for two things – the value being driven onto P4, and the value seen on P4. This inevitably leads to issues.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It has the data bus for the three devices connected to port4. Its setting the direction/ddr appropriately for the port and either reading or writing the data bus value before then driving the device control lines via the port3. I had it like this as this is how it would be working for the real hardware. Is this something that needs separating more for how mame handles things?

Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It will only “work” like this if you assume the program is well-behaved and does things in a particular order. In reality, the logic levels visible on the port is some combination of the levels driven by all the devices driving the lines, which may be more than one if the software is badly behaved.

You also need to consider that the levels driven by the peripherals won’t “stick” when the peripherals are deselected. It’s a lot easier to keep the levels driven by each device separately, and AND them all together when you need to get the overall levels visible on the bus.

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I understand what you're saying but there is one piece of firmware running this thing that doesn't change and it works right now. And what it's trying to do (read and write the AY registers) is discrete and well defined. There is no need for the whole AND thing.

Comment on lines 197 to 225
if (BIT(data, 2)) // BDIR
{
if (BIT(data, 3)) // BC1
m_ay1->address_w(m_data);
else
m_ay1->data_w(m_data);
}
else if (!BIT(data, 3))
m_data = m_ay1->data_r();
}

if (!BIT(data, 4)) // AY2 *CS
{
if (BIT(data, 2)) // BDIR
{
if (BIT(data, 3)) // BC1
m_ay2->address_w(m_data);
else
m_ay2->data_w(m_data);
}
else if(!BIT(data, 3))
m_data = m_ay2->data_r();
}

if (!BIT(data, 0)) //5220 read
m_data = m_tms->status_r();

if (!BIT(data, 1)) //5220 write
m_tms->data_w(m_data);
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

You really need to detect active edges on these data bits. If the software writes the same value to the bit twice in a row, it won’t cause an additional write. For example, just looking at the TMS5220:

    ...

    if (BIT(~data & m_p3_out, 0)) // 5220 read
        m_tms_data = m_tms->status_r();
    else if (BIT(data, 0)) // 5220 deselected
        m_tms_data = 0xff;

    if (BIT(~data & m_p3_out, 1)) //5220 write
        m_tms->data_w(/* calculate actual levels from all devices driving the lines here */);

    m_p3_out = data;

Also, what exactly are bits 4 and 5 connected to? The AY-3-891x chips don’t have a chip select input as such. They have BC1, BC2 and BDIR inputs, but the only time the chip doesn’t do anything is when BC1 and BDIR are both low. If either BC1 or BDIR is high, the chip responds. So I don’t see how the logic here can be correct, unless there are additional AND gates to force the corresponding BDIR low if bit 5 or bit 4 is low.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

There is a chip select input on the AY8913 version of these, and the Cricket is using the AP8913 variant. Here is the not quite finished schematic for it. It has a few wrong symbols for caps and needs the power supply checked, but otherwise its fine. Will give you an idea how its hooked up.
cricket.pdf

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

3 participants