[DRAFT] Use Systemrdl to describe the registers interface

data/sonata_udp.rdl

@@ -0,0 +1,50 @@
+/* Copyright lowRISC contributors.
+* Licensed under the Apache License, Version 2.0; see LICENSE for details.
+* SPDX-License-Identifier: Apache-2.0
+*/
+
+/* Indicates what the signal is used for.
+ */
+enum SigType {
+  None; 
+  PadInOut; // Signal is a pad for In and Out. i.e: i2c.sda.
+  PadInput; // Signal is a pad for Input. i.e: uart.rx
+  PadOutput; // Signal is a pad for Output. i.e: uart.tx
+  Interrupt;// Signal is an Interrupt
+};
+
+/* Indicates what the signal will be used for.
+ */
+property sigtype {
+  type = SigType;
+  component = signal;
+  default = SigType::None;
+};
+
+enum IoCombine {
+  None;
+  Mux;
+  And;
+  Or;
+};
+
+/* 
+ */
+property io_combine {
+  type = IoCombine;
+  component = signal;
+  default = IoCombine::None;
+};
+
+struct parameter {
+  string type_;
+  string name;
+  string value;
+};
+
+property xbar {
+  type = parameter[];
+  component = addrmap|mem;
+  default = '{};
+};
+

data/top.rdl

@@ -0,0 +1,79 @@
+/* Copyright lowRISC contributors.
+* Licensed under the Apache License, Version 2.0; see LICENSE for details.
+* SPDX-License-Identifier: Apache-2.0
+*/
+
+`include "udp.rdl"
+`include "sonata_udp.rdl"
+`include "../rtl/ip/system_info/data/system_info.rdl"
+`include "../rtl/ip/spi/data/spi.rdl"
+`include "../rtl/ip/rgbled_ctrl/data/rgbled_ctrl.rdl"
+`include "../rtl/ip/pwm/data/pwm.rdl"
+`include "../rtl/ip/gpio/data/gpio.rdl"
+`include "../rtl/ip/usbdev/data/usbdev.rdl"
+`include "../rtl/ip/i2c/data/i2c.rdl"
+`include "../rtl/ip/uart/data/uart.rdl"
+`include "../rtl/ip/xadc/data/xadc.rdl"
+`include "../rtl/ip/rev_ctl/data/rev_ctl.rdl"
+`include "../rtl/system/data/rv_plic.rdl"
+`include "../rtl/system/data/pinmux.rdl"
+`include "../rtl/system/data/rv_timer.rdl"
+
+addrmap top_sonata {
+  external mem sram {
+    mementries = 0x20000; memwidth=8;
+    clk_input = '{ "clk_sys_i" };
+    rst_input = '{ "rst_sys_ni" };
+  } SRAM @ 0x00100000;
+
+  external mem hyperram {
+    mementries = 0x100000; memwidth=8;
+    clk_input = '{ "clk_sys_i" };
+    rst_input = '{ "rst_sys_ni" };
+  } HYPERRAM @ 0x40000000;
+
+  external mem rev_tag {
+    mementries = 0x800; memwidth=8;
+    clk_input = '{ "clk_sys_i" };
+    rst_input = '{ "rst_sys_ni" };
+  } REV_TAG @ 0x30000000;
+
+  gpio GPIO[6] @ 0x80000000 += 0x40;
+
+  pwm PWM[1] @ 0x80001000 += 0x1000;
+
+  pinmux PINMUX @ 0x80005000;
+
+  rgbled_ctrl RGBLED_CTRL @ 0x80009000;
+
+  rev_ctl HW_REV @ 0x8000A000;
+
+  xadc XADC @ 0x8000B000;
+
+  system_info SYSTEM_INFO @ 0x8000C000;
+
+  rv_timer TIMER @ 0x80040000;
+
+  uart uart[3] @ 0x80100000 += 0x1000;
+
+  i2c I2C[2] @ 0x80200000 += 0x1000;
+
+  spi SPI_LCD @ 0x80300000;
+
+  spi SPI_ETHMAC @ 0x80301000;
+
+  spi SPI[3]  @ 0x80302000 += 0x1000;
+
+  usbdev USBDEV @ 0x80400000;
+
+  // This block is overaligned to 0x0800_0000 bytes since OpenTitan RV_PLIC block expects it.
+  rv_plic RV_PLIC @ 0x88000000;
+
+  external mem dgb_dev { 
+    mementries = 0x1000; memwidth=8;
+    xbar = '{ parameter'{ type_: "bool", name: "pipeline", value:  "true" }};
+    clk_input = '{ "clk_sys_i" };
+    rst_input = '{ "rst_sys_ni" };
+  } DBG_DEV @ 0xB0000000;
+};
+

data/top_config.toml

@@ -1,59 +1,3 @@
-[[blocks]]
-name = "gpio"
-instances = 5 # RPi, Ard, Pmod0, Pmod1, PmodC
-ios = [
-  {
-    name = "ios",
-    type = "inout",
-    combine = "mux",
-    length = 32
-  },
-]
-memory_start = 0x80000040
-memory_size  = 0x00000040
-
-[[blocks]]
-name = "pwm"
-instances = 1
-ios = [{ name = "out", type = "output", length = 7 }]
-memory_start = 0x80001000
-memory_size  = 0x00001000
-xbar = { pipeline = "true", req_fifo_pass = "false", rsp_fifo_pass = "false" }
-
-[[blocks]]
-name = "uart"
-instances = 3
-ios = [
-  { name = "rx", type = "input", default = 1 },
-  { name = "tx", type = "output" },
-]
-memory_start = 0x80100000
-memory_size  = 0x00001000
-xbar = { pipeline = "true", req_fifo_pass = "false", rsp_fifo_pass = "false" }
-
-[[blocks]]
-name = "i2c"
-instances = 2
-ios = [
-  { name = "scl", type = "inout", combine = "and" },
-  { name = "sda", type = "inout", combine = "and" },
-]
-memory_start = 0x80200000
-memory_size  = 0x00001000
-xbar = { pipeline = "true", req_fifo_pass = "false", rsp_fifo_pass = "false" }
-
-[[blocks]]
-name = "spi"
-instances = 3
-ios = [
-  { name = "cipo", type = "input", default = 0 },
-  { name = "copi", type = "output" },
-  { name = "sclk", type = "output" },
-  { name = "cs", type = "output", length = 4 },
-]
-memory_start = 0x80302000
-memory_size  = 0x00001000
-
 # UARTS
 [[pins]]
 name = "ser0_tx"

data/udp.rdl

@@ -0,0 +1,119 @@
+/* Copyright lowRISC contributors (OpenTitan project).
+ * Licensed under the Apache License, Version 2.0; see LICENSE for details.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * 4-bits boolean values
+ */
+enum MultiBitBool4 {
+  True = 0x6;
+  False = 0x9;
+};
+
+/**
+ * 8-bits boolean values
+ */
+enum MultiBitBool8 {
+  True = 0x96;
+  False = 0x69;
+};
+
+/**
+ * 12-bits boolean values
+ */
+enum MultiBitBool12 {
+  True = 0x696;
+  False = 0x969;
+};
+
+/**
+ * 16-bits boolean values
+ */
+enum MultiBitBool16 {
+  True = 0x9696;
+  False = 0x6969;
+};
+
+/**
+ * 20-bits boolean values
+ */
+enum MultiBitBool20 {
+  True = 0x69696;
+  False = 0x96969;
+};
+
+/**
+ * 24-bits boolean values
+ */
+enum MultiBitBool24 {
+  True = 0x969696;
+  False = 0x696969;
+};
+
+/**
+ * 28-bits boolean values
+ */
+enum MultiBitBool28 {
+  True = 0x6969696;
+  False = 0x9696969;
+};
+
+/**
+ * 32-bits boolean values
+ */
+enum MultiBitBool32 {
+  True = 0x96969696;
+  False = 0x69696969;
+};
+
+/**
+ * true if hardware uses `re` signal, which is latched signal of software read pulse.
+ * The standard SystemRDL property `swacc` cannot be used here because `swacc = hwre | swmod`.
+ */
+property hwre {
+  type = boolean;
+  component = reg;
+  default = false;
+};
+
+/* If it is true, the register will be implemented using the prim_subreg_shadow module.
+ * Shadow registers are a mechanism to guard sensitive registers against this specific
+ * type of attack. They come at a cost of increased area, and a modified SW interaction.
+ */
+property shadowed {
+  type = boolean;
+  component = reg;
+  default = false;
+};
+
+/* Indicates the register must cross to a different clock domain before use.
+ * The value shown here should correspond to one of the module’s clocks.
+ */
+property async_clk {
+  type = boolean;
+  component = reg;
+  default = false;
+};
+
+property clk_input {
+  type = string[];
+  component = addrmap|regfile|reg|mem;
+  default = '{};
+};
+
+/* If true, integrity bits are passed through directly from the memory.
+ */
+property integrity_bypass {
+  type = boolean;
+  component = mem;
+  default = false;
+};
+
+property rst_input {
+  type = string[];
+  component = addrmap|regfile|reg|mem;
+  default = '{};
+};
+
+