[darjeeling,dv] Enable more system level tests

[Razer6]

Those tests are already ported, let's enable them.

[rswarbrick]

Seems sensible to me (assuming that you've run them at your end :-D)

[Razer6]

Even better, they are now in CI :)

### Test Results
|  Stage  |               Name               | Tests                            |  Max Job Runtime  |  Simulated Time  |  Passing  |  Total  |  Pass Rate  |
|:-------:|:--------------------------------:|:---------------------------------|:-----------------:|:----------------:|:---------:|:-------:|:-----------:|
|   V2    |      chip_rv_dm_lc_disabled      | chip_rv_dm_lc_disabled           |      13.467m      |     13.490ms     |     1     |    1    |  100.00 %   |
|   V2    |    chip_sw_clkmgr_idle_trans     | chip_sw_kmac_idle                |      5.267m       |     3.480ms      |     1     |    1    |  100.00 %   |
|   V2    |      chip_sw_clkmgr_jitter       | chip_sw_clkmgr_jitter            |      5.717m       |     3.449ms      |     1     |    1    |  100.00 %   |
|   V2    |      chip_sw_rstmgr_sw_rst       | chip_sw_rstmgr_sw_rst            |      4.850m       |     3.472ms      |     1     |    1    |  100.00 %   |
|   V2    |    chip_sw_lc_ctrl_broadcast     | chip_sw_rom_ctrl_integrity_check |      10.850m      |     10.938ms     |     1     |    1    |  100.00 %   |
|         |                                  | chip_prim_tl_access              |      13.850m      |     13.520ms     |     1     |    1    |  100.00 %   |
|         |                                  | chip_rv_dm_lc_disabled           |      13.467m      |     13.490ms     |     1     |    1    |  100.00 %   |
|   V2    |       chip_sw_aes_entropy        | chip_sw_aes_entropy              |      5.133m       |     3.488ms      |     1     |    1    |  100.00 %   |
|   V2    |         chip_sw_hmac_enc         | chip_sw_hmac_enc                 |      5.617m       |     3.594ms      |     1     |    1    |  100.00 %   |
|   V2    |         chip_sw_kmac_enc         | chip_sw_kmac_mode_cshake         |      5.167m       |     3.519ms      |     1     |    1    |  100.00 %   |
|         |                                  | chip_sw_kmac_mode_kmac           |      7.000m       |     3.751ms      |     1     |    1    |  100.00 %   |
|   V2    |        chip_sw_kmac_idle         | chip_sw_kmac_idle                |      5.267m       |     3.480ms      |     1     |    1    |  100.00 %   |
|   V2    |        chip_sw_rom_access        | chip_sw_rom_ctrl_integrity_check |      10.850m      |     10.938ms     |     1     |    1    |  100.00 %   |
|   V2    | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check |      10.850m      |     10.938ms     |     1     |    1    |  100.00 %   |
|   V2    |   chip_sw_otp_ctrl_lc_signals    | chip_prim_tl_access              |      13.850m      |     13.520ms     |     1     |    1    |  100.00 %   |
|   V2    |    chip_sw_otp_prim_tl_access    | chip_prim_tl_access              |      13.850m      |     13.520ms     |     1     |    1    |  100.00 %   |
|   V2    |    chip_sw_ast_sys_clk_jitter    | chip_sw_clkmgr_jitter            |      5.717m       |     3.449ms      |     1     |    1    |  100.00 %   |
|   V2    |          chip_lc_scrap           | chip_sw_lc_ctrl_rand_to_scrap    |      4.933m       |     4.035ms      |     1     |    1    |  100.00 %   |
|   V2    |       chip_lc_test_locked        | chip_rv_dm_lc_disabled           |      13.467m      |     13.490ms     |     1     |    1    |  100.00 %   |
|   V2    |                                  | **TOTAL**                        |                   |                  |    11     |   11    |  100.00 %   |
|         |                                  | **TOTAL**                        |                   |                  |    11     |   11    |  100.00 %   |