[sw,opentitanlib] QEMU I2C transport and target mode test #28450
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| let i2c = match find_chardev(&chardevs, "i2c0") { |
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Any reason we can't expose I2C1 and I2C2 in QEMU as well?
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No reason at all, I can make all 3.
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Might be nice to add test coverage for those as well if it isn't too hard (I would imagine it's just a loop on the test but maybe it isn't that simple).
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It could be done, but that would involve duplicating the emulated device state and I2C target mode and IRQ setup for each bus.
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I think this small duplication is ok (done in other I2C tests as well) but maybe instead of duplicating the emulated device state you could instead add a function for resetting the state between each I2C test run?
| "//hw/top_earlgrey:sim_qemu_rom_with_fake_keys": None, | ||
| }, |
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I think this test should also work in ROM_EXT exec envs now, so maybe add:
| "//hw/top_earlgrey:sim_qemu_rom_with_fake_keys": None, | |
| }, | |
| "//hw/top_earlgrey:sim_qemu_rom_with_fake_keys": None, | |
| "//hw/top_earlgrey:sim_qemu_sival_rom_ext": None, | |
| }, |
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Thanks @ziuziakowska for this great work.
I left some suggestions to be considered.
I believe that this a valid new test, and I don't see a reason for not running it on the FPGA and Silicon as well.
This implements a I2C transport for QEMU. The transport uses a PTY to communicate with a `ot_i2c_transport` device to issue transfers to devices on the internal QEMU I2C buses. See `docs/opentitan/i2c_transport.md` in QEMU for more imformation on the protocol. Signed-off-by: Alice Ziuziakowska <[email protected]>
This creates a test for Opentitan's I2C target mode for QEMU, using a test harness that utilises the I2C QEMU transport implemented in the previous commit. The tested device emulates a simple "memory" device on the I2C bus. The device consists of a 256-byte "memory". On a write transfer to the device, the first byte sets the "pointer" to within the memory where subsequent bytes are written to or read from. This value is incremented after each written or read byte. During a read transfer, bytes from memory to be read are buffered in the TX FIFO, which is refilled if its fill level drops below a threshold. The test harness uses the I2C transport device in QEMU to issue transfers to write to and read from the emulated memory device. Signed-off-by: Alice Ziuziakowska <[email protected]>
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This implements the I2C transport for QEMU in
opentitanlib, and creates a test of Opentitan's I2C target mode that uses the functionality in a test harness.In this test, a simple "memory" device is emulated by software, and can be interacted with over the I2C bus. The test harness performs transfers with the device, through the new OT I2C transport device in QEMU to interact with devices on the internal I2C bus, namely OT I2C. The software also listens to another I2C address, and exits the test successfully when written to with a magic value.
This depends on the I2C transport protocol and device implementation in QEMU - see lowRISC/qemu#190.
For now the test is QEMU-specific, but in theory this could also run on any other execution environments which already have an I2C transport implementation in
opentitanlib, with little adaptation.