[AArch64] Have convertToNonFlagSettingOpc and getNonFlagSettingVariant have parity with each other

[AZero13]

They are both missing entries from each other.

[llvmbot]

@llvm/pr-subscribers-llvm-globalisel

@llvm/pr-subscribers-backend-aarch64

Author: AZero13 (AZero13)

Changes

They are both missing entries from each other.

---

Full diff: https://github.com/llvm/llvm-project/pull/150085.diff

3 Files Affected:

• (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.cpp (+8)
• (modified) llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp (+8)
• (modified) llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-dead-cc-defs-in-fcmp.mir (+48)

diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 996b0edd24200..54729fcbfc3e5 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -1432,6 +1432,14 @@ static unsigned convertToNonFlagSettingOpc(const MachineInstr &MI) {
     return MIDefinesZeroReg ? AArch64::SUBSXrs : AArch64::SUBXrs;
   case AArch64::SUBSXrx:
     return AArch64::SUBXrx;
+  case AArch64::SBCSXr:
+    return AArch64::SBCXr;
+  case AArch64::SBCSWr:
+    return AArch64::SBCWr;
+  case AArch64::ADCSXr:
+    return AArch64::ADCXr;
+  case AArch64::ADCSWr:
+    return AArch64::ADCWr;
   }
 }
 
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp
index 4bd025da636ca..5b31ed2b772cc 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp
@@ -71,6 +71,10 @@ unsigned getNonFlagSettingVariant(unsigned Opc) {
     return AArch64::SUBXrs;
   case AArch64::SUBSWrs:
     return AArch64::SUBWrs;
+  case AArch64::SUBSWrx:
+    return AArch64::SUBWrx;
+  case AArch64::SUBSXrx:
+    return AArch64::SUBXrx;
   case AArch64::SUBSXri:
     return AArch64::SUBXri;
   case AArch64::SUBSWri:
@@ -83,6 +87,10 @@ unsigned getNonFlagSettingVariant(unsigned Opc) {
     return AArch64::ADDXrs;
   case AArch64::ADDSWrs:
     return AArch64::ADDWrs;
+  case AArch64::ADDSWrx:
+    return AArch64::ADDWrx;
+  case AArch64::ADDSXrx:
+    return AArch64::ADDXrx;
   case AArch64::ADDSXri:
     return AArch64::ADDXri;
   case AArch64::ADDSWri:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-dead-cc-defs-in-fcmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-dead-cc-defs-in-fcmp.mir
index 0b9c72f6358cd..8de6afa2e64e6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-dead-cc-defs-in-fcmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-dead-cc-defs-in-fcmp.mir
@@ -164,6 +164,54 @@ body:             |
     RET_ReallyLR implicit $x0
 ...
 ---
+name:            test_impdef_addsrx
+alignment:       4
+legalized:       true
+regBankSelected: true
+selected:        true
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    liveins: $x0, $w1
+    ; CHECK-LABEL: name: test_impdef_addsrx
+    ; CHECK: liveins: $x0, $w1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: [[ADDXrx:%[0-9]+]]:gpr64common = ADDXrx [[COPY]], [[COPY1]], 18
+    ; CHECK-NEXT: $x0 = COPY [[ADDXrx]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $x0
+    %1:gpr64sp = COPY $x0
+    %2:gpr32 = COPY $w1
+    %4:gpr64 = ADDSXrx %1, %2, 18, implicit-def $nzcv
+    $x0 = COPY %4
+    RET_ReallyLR implicit $x0
+...
+---
+name:            test_impdef_subsrx
+alignment:       4
+legalized:       true
+regBankSelected: true
+selected:        true
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    liveins: $x0, $w1
+    ; CHECK-LABEL: name: test_impdef_subsrx
+    ; CHECK: liveins: $x0, $w1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: [[SUBXrx:%[0-9]+]]:gpr64common = SUBXrx [[COPY]], [[COPY1]], 18
+    ; CHECK-NEXT: $x0 = COPY [[SUBXrx]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $x0
+    %1:gpr64sp = COPY $x0
+    %2:gpr32 = COPY $w1
+    %4:gpr64 = SUBSXrx %1, %2, 18, implicit-def $nzcv
+    $x0 = COPY %4
+    RET_ReallyLR implicit $x0
+...
+---
 name:            test_impdef_subsw
 alignment:       4
 legalized:       true