[DemandedBits] Support non-constant shift amounts #148880

karouzakisp · 2025-07-15T16:11:49Z

This patch adds support for the shift operators to handle non-constant shift operands.

This is done by supporting shift operators to handle non constant shift amount.

github-actions · 2025-07-15T16:12:10Z

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llvmbot · 2025-07-15T16:12:42Z

@llvm/pr-subscribers-llvm-analysis

Author: Panagiotis K (karouzakisp)

Changes

This is part of a larger PR: #148853
To improve the DemandedBits Analysis.

Here we add support to the shift operators to handle non-constant shift operands.

Full diff: https://github.com/llvm/llvm-project/pull/148880.diff

2 Files Affected:

(modified) llvm/lib/Analysis/DemandedBits.cpp (+46)
(modified) llvm/test/Analysis/DemandedBits/shl.ll (+47-1)

diff --git a/llvm/lib/Analysis/DemandedBits.cpp b/llvm/lib/Analysis/DemandedBits.cpp
index 6694d5cc06c8c..2d30575c19130 100644
--- a/llvm/lib/Analysis/DemandedBits.cpp
+++ b/llvm/lib/Analysis/DemandedBits.cpp
@@ -36,6 +36,7 @@
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/KnownBits.h"
+#include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 #include <algorithm>
 #include <cstdint>
@@ -183,6 +184,17 @@ void DemandedBits::determineLiveOperandBits(
           AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1);
         else if (S->hasNoUnsignedWrap())
           AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
+      } else {
+        ComputeKnownBits(BitWidth, UserI->getOperand(1), nullptr);
+        unsigned Min = Known.getMinValue().getLimitedValue(BitWidth - 1);
+        unsigned Max = Known.getMaxValue().getLimitedValue(BitWidth - 1);
+        // similar to Lshr case
+        AB = (AOut.lshr(Min) | AOut.lshr(Max));
+        const auto *S = cast<ShlOperator>(UserI);
+        if (S->hasNoSignedWrap())
+          AB |= APInt::getHighBitsSet(BitWidth, Max + 1);
+        else if (S->hasNoUnsignedWrap())
+          AB |= APInt::getHighBitsSet(BitWidth, Max);
       }
     }
     break;
@@ -197,6 +209,19 @@ void DemandedBits::determineLiveOperandBits(
         // (they must be zero).
         if (cast<LShrOperator>(UserI)->isExact())
           AB |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
+      } else {
+        ComputeKnownBits(BitWidth, UserI->getOperand(1), nullptr);
+        unsigned Min = Known.getMinValue().getLimitedValue(BitWidth - 1);
+        unsigned Max = Known.getMaxValue().getLimitedValue(BitWidth - 1);
+        // Suppose AOut == 0b0000 0011
+        // [min, max] = [1, 3]
+        // shift by 1 we get 0b0000 0110
+        // shift by 2 we get 0b0000 1100
+        // shift by 3 we get 0b0001 1000
+        // we take the or here because need to cover all the above possibilities
+        AB = (AOut.shl(Min) | AOut.shl(Max));
+        if (cast<LShrOperator>(UserI)->isExact())
+          AB |= APInt::getLowBitsSet(BitWidth, Max);
       }
     }
     break;
@@ -217,6 +242,27 @@ void DemandedBits::determineLiveOperandBits(
         // (they must be zero).
         if (cast<AShrOperator>(UserI)->isExact())
           AB |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
+      } else {
+        ComputeKnownBits(BitWidth, UserI->getOperand(1), nullptr);
+        unsigned Min = Known.getMinValue().getLimitedValue(BitWidth - 1);
+        unsigned Max = Known.getMaxValue().getLimitedValue(BitWidth - 1);
+        AB = (AOut.shl(Min) | AOut.shl(Max));
+
+        if (Max) {
+          // Suppose AOut = 0011 1100
+          // [min, max] = [1, 3]
+          // ShiftAmount = 1 : Mask is 1000 0000
+          // ShiftAmount = 2 : Mask is 1100 0000
+          // ShiftAmount = 3 : Mask is 1110 0000
+          // The Mask with Max covers every case in [min, max],
+          // so we are done
+          if ((AOut & APInt::getHighBitsSet(BitWidth, Max)).getBoolValue())
+            AB.setSignBit();
+        }
+        // If the shift is exact, then the low bits are not dead
+        // (they must be zero).
+        if (cast<AShrOperator>(UserI)->isExact())
+          AB |= APInt::getLowBitsSet(BitWidth, Max);
       }
     }
     break;
diff --git a/llvm/test/Analysis/DemandedBits/shl.ll b/llvm/test/Analysis/DemandedBits/shl.ll
index e41f5f4107735..c3313a93c1e85 100644
--- a/llvm/test/Analysis/DemandedBits/shl.ll
+++ b/llvm/test/Analysis/DemandedBits/shl.ll
@@ -57,10 +57,56 @@ define i8 @test_shl(i32 %a, i32 %b) {
 ; CHECK-DAG:  DemandedBits: 0xff for %shl.t = trunc i32 %shl to i8
 ; CHECK-DAG:  DemandedBits: 0xff for %shl in %shl.t = trunc i32 %shl to i8
 ; CHECK-DAG:  DemandedBits: 0xff for %shl = shl i32 %a, %b
-; CHECK-DAG:  DemandedBits: 0xffffffff for %a in %shl = shl i32 %a, %b
+; CHECK-DAG:  DemandedBits: 0xff for %a in %shl = shl i32 %a, %b
 ; CHECK-DAG:  DemandedBits: 0xffffffff for %b in %shl = shl i32 %a, %b
 ;
   %shl = shl i32 %a, %b
   %shl.t = trunc i32 %shl to i8
   ret i8 %shl.t
 }
+
+define i8 @test_shl_var_amount(i32 %a, i32 %b){
+; CHECK-LABEL: 'test_shl_var_amount'
+; CHECK-DAG: DemandedBits: 0xff for   %5 = trunc i32 %4 to i8
+; CHECK-DAG: DemandedBits: 0xff for %4 in   %5 = trunc i32 %4 to i8
+; CHECK-DAG: DemandedBits: 0xff for   %4 = shl i32 %1, %3
+; CHECK-DAG: DemandedBits: 0xff for %1 in   %4 = shl i32 %1, %3
+; CHECK-DAG: DemandedBits: 0xffffffff for %3 in   %4 = shl i32 %1, %3
+; CHECK-DAG: DemandedBits: 0xff for   %2 = trunc i32 %1 to i8
+; CHECK-DAG: DemandedBits: 0xff for %1 in   %2 = trunc i32 %1 to i8
+; CHECK-DAG: DemandedBits: 0xffffffff for   %3 = zext i8 %2 to i32
+; CHECK-DAG: DemandedBits: 0xff for %2 in   %3 = zext i8 %2 to i32
+; CHECK-DAG: DemandedBits: 0xff for   %1 = add nsw i32 %a, %b
+; CHECK-DAG: DemandedBits: 0xff for %a in   %1 = add nsw i32 %a, %b
+; CHECK-DAG: DemandedBits: 0xff for %b in   %1 = add nsw i32 %a, %b
+;
+  %1 = add nsw i32 %a, %b
+  %2 = trunc i32 %1 to i8
+  %3 = zext i8 %2 to i32
+  %4 = shl i32 %1, %3
+  %5 = trunc i32 %4 to i8
+  ret i8 %5
+}
+
+define i8 @test_shl_var_amount_nsw(i32 %a, i32 %b){
+ ; CHECK-LABEL 'test_shl_var_amount_nsw'
+ ; CHECK-DAG: DemandedBits: 0xff for   %5 = trunc i32 %4 to i8
+ ; CHECK-DAG: DemandedBits: 0xff for %4 in   %5 = trunc i32 %4 to i8
+ ; CHECK-DAG: DemandedBits: 0xff for   %4 = shl nsw i32 %1, %3
+ ; CHECK-DAG: DemandedBits: 0xffffffff for %1 in   %4 = shl nsw i32 %1, %3
+ ; CHECK-DAG: DemandedBits: 0xffffffff for %3 in   %4 = shl nsw i32 %1, %3
+ ; CHECK-DAG: DemandedBits: 0xffffffff for   %3 = zext i8 %2 to i32
+ ; CHECK-DAG: DemandedBits: 0xff for %2 in   %3 = zext i8 %2 to i32
+ ; CHECK-DAG: DemandedBits: 0xff for   %2 = trunc i32 %1 to i8
+ ; CHECK-DAG: DemandedBits: 0xff for %1 in   %2 = trunc i32 %1 to i8
+ ; CHECK-DAG: DemandedBits: 0xffffffff for   %1 = add nsw i32 %a, %b
+ ; CHECK-DAG: DemandedBits: 0xffffffff for %a in   %1 = add nsw i32 %a, %b
+ ; CHECK-DAG: DemandedBits: 0xffffffff for %b in   %1 = add nsw i32 %a, %b
+ ;
+  %1 = add nsw i32 %a, %b
+  %2 = trunc i32 %1 to i8
+  %3 = zext i8 %2 to i32
+  %4 = shl nsw i32 %1, %3
+  %5 = trunc i32 %4 to i8
+  ret i8 %5
+}

karouzakisp · 2025-07-15T16:20:59Z

@nikic @artagnon @jayfoad Could you please review? Thanks

artagnon

Missing coverage for lshr and ashr? Could you kindly add tests for them?

topperc · 2025-07-15T16:30:06Z

Missing tests for right shifts?

artagnon · 2025-07-15T16:33:26Z

Kindly note that we only have a squash-and-merge. As a result:

Your commit message should be filled into the PR, including the title. The PR's title and body will be used as the commit message, and the text in your commit will be discarded when landing.
Kindly add additional changes as separate commits, and avoid force-pushing except when a rebase is required.

dtcxzyw

Please provide the alive2 proof. See also my previous comment #148853 (review)

llvm/lib/Analysis/DemandedBits.cpp

topperc · 2025-07-15T17:46:57Z

llvm/lib/Analysis/DemandedBits.cpp

+        // shift by 2 we get 0b0000 1100
+        // shift by 3 we get 0b0001 1000
+        // we take the or here because need to cover all the above possibilities
+        AB = (AOut.shl(Min) | AOut.shl(Max));


Doesn't this need to be the OR of all possible shift amounts between Min and Max? Not just the end points. Using the end points only works if the set bits in AOut are contiguous.

Doesn't this need to be the OR of all possible shift amounts between Min and Max? Not just the end points. Using the end points only works if the set bits in AOut are contiguous.

Yes that's correct. I just added a function GetShiftedRange to shift between Min and Max

llvm/lib/Analysis/DemandedBits.cpp

…dle non continued bits for AOut

karouzakisp · 2025-07-15T20:56:56Z

Missing tests for right shifts?

I just added the tests

karouzakisp · 2025-07-15T21:17:12Z

Please provide the alive2 proof. See also my previous comment #148853 (review)

I am not certain which transformation I should verify. Maybe the one on your previous comment?

artagnon · 2025-07-15T21:27:01Z

Please provide the alive2 proof. See also my previous comment #148853 (review)

I am not certain which transformation I should verify. Maybe the one on your previous comment?

I think what we want verified is the algorithm of the analysis itself, not a particular transformation: if can express the code you wrote for DemandedBits in a language that Alive2 can verify, that would be great (this isn't exactly straight-forward, but @dtcxzyw left some hints). Think about it, and try it out: we'll help out.

dtcxzyw

Miscompilation reproducer: https://alive2.llvm.org/ce/z/bSBzWM

; bin/opt -passes=bdce test.ll -S
define i16 @src(i32 range(i32 0, 2) %x) {
entry:
  %or = or i32 0, 48
  %shl = shl i32 %or, %x
  %trunc = trunc i32 %shl to i16
  ret i16 %trunc
}

define i16 @tgt(i32 range(i32 0, 2) %x) {
entry:
  %shl = shl i32 0, %x
  %trunc = trunc i32 %shl to i16
  ret i16 %trunc
}

…ore checks

karouzakisp · 2025-07-16T20:11:34Z

Miscompilation reproducer: https://alive2.llvm.org/ce/z/bSBzWM

; bin/opt -passes=bdce test.ll -S
define i16 @src(i32 range(i32 0, 2) %x) {
entry:
  %or = or i32 0, 48
  %shl = shl i32 %or, %x
  %trunc = trunc i32 %shl to i16
  ret i16 %trunc
}

define i16 @tgt(i32 range(i32 0, 2) %x) {
entry:
  %shl = shl i32 0, %x
  %trunc = trunc i32 %shl to i16
  ret i16 %trunc
}

Fixed, Alive verifications coming soon. Hopefully this week!

karouzakisp · 2025-07-18T14:07:27Z

Please provide the alive2 proof. See also my previous comment #148853 (review)

@dtcxzyw Here are the alive2 proofs -->
https://alive2.llvm.org/ce/z/SxgY_5

Please note that since my transformation contains a loop and the Alive syntax doesn't permit loops, I added various ranges.

Please let me know if it's okay.

@artagnon, Please let me know what you think.

dtcxzyw · 2025-07-19T15:10:22Z

my transformation contains a loop and the Alive syntax doesn't permit loops

You can use a smaller integer bitwidth (e.g., i4/i8), then unroll the loop with -src-unroll=8 -tgt-unroll=8.

karouzakisp · 2025-07-19T17:13:54Z

my transformation contains a loop and the Alive syntax doesn't permit loops

You can use a smaller integer bitwidth (e.g., i4/i8), then unroll the loop with -src-unroll=8 -tgt-unroll=8.

Thanks for the tip. Here is the updated proof --> https://alive2.llvm.org/ce/z/tCvUT6

dtcxzyw · 2025-07-20T06:24:51Z

my transformation contains a loop and the Alive syntax doesn't permit loops

You can use a smaller integer bitwidth (e.g., i4/i8), then unroll the loop with -src-unroll=8 -tgt-unroll=8.

Thanks for the tip. Here is the updated proof --> https://alive2.llvm.org/ce/z/tCvUT6

In your proof, the range of shamt is not taken into account. Updated: https://alive2.llvm.org/ce/z/n4hgkX
~~Can you please add proofs for shl nsw/shl nuw/lshr/lshr exact/ashr/ashr exact?~~
Can you please add proofs for lshr/ashr?
Then you should paste the links into the PR description.

dtcxzyw · 2025-07-20T06:10:27Z

llvm/lib/Analysis/DemandedBits.cpp

@@ -76,6 +76,16 @@ void DemandedBits::determineLiveOperandBits(
          computeKnownBits(V2, Known2, DL, &AC, UserI, &DT);
        }
      };
+  auto GetShiftedRange = [&](unsigned const Min, unsigned const Max,


Suggested change

auto GetShiftedRange = [&](unsigned const Min, unsigned const Max,

auto GetShiftedRange = [&](unsigned Min, unsigned Max,

dtcxzyw · 2025-07-20T06:15:49Z

llvm/lib/Analysis/DemandedBits.cpp

+        unsigned Max = Known.getMaxValue().getLimitedValue(BitWidth - 1);
+        // Suppose AOut == 0b0000 1001
+        // [min, max] = [1, 3]
+        // shift by 1 we get 0b0001 00100


Suggested change

// shift by 1 we get 0b0001 00100

// shift by 1 we get 0b0001 0010

[LLVM] Enhance shift operators in the Demanded Bits Analysis

b802455

This is done by supporting shift operators to handle non constant shift amount.

llvmbot added the llvm:analysis Includes value tracking, cost tables and constant folding label Jul 15, 2025

artagnon requested review from artagnon, jayfoad and nikic July 15, 2025 16:22

artagnon reviewed Jul 15, 2025

View reviewed changes

artagnon requested a review from dtcxzyw July 15, 2025 16:50

dtcxzyw mentioned this pull request Jul 15, 2025

Task submission dtcxzyw/llvm-opt-benchmark#1312

Open

zyw-bot mentioned this pull request Jul 15, 2025

pre-commit: PR148880 dtcxzyw/llvm-opt-benchmark#2573

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llvm/lib/Analysis/DemandedBits.cpp Outdated Show resolved Hide resolved

dtcxzyw mentioned this pull request Jul 15, 2025

Fuzz PR148880 dtcxzyw/llvm-fuzz-service#103

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topperc reviewed Jul 15, 2025

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llvm/lib/Analysis/DemandedBits.cpp Show resolved Hide resolved

[LLVM] created new tests for lshr and ashr, and updated the Range han…

289fb1c

…dle non continued bits for AOut

karouzakisp changed the title ~~[LLVM] Improve the DemandedBits Analysis~~ [LLVM] Improve the shift operators of the DemandedBits Analysis Jul 15, 2025

removed comment

3a4d65e

nikic changed the title ~~[LLVM] Improve the shift operators of the DemandedBits Analysis~~ [DemandedBits] Support non-constant shift amounts Jul 16, 2025

dtcxzyw reviewed Jul 16, 2025

View reviewed changes

fixed or-->trunc->shl error, by updating the GetShiftedRange, needs m…

4fbabd6

…ore checks

added more range tests

23cea68

zyw-bot mentioned this pull request Jul 20, 2025

pre-commit: PR148880 dtcxzyw/llvm-opt-benchmark#2586

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	auto GetShiftedRange = [&](unsigned const Min, unsigned const Max,
	auto GetShiftedRange = [&](unsigned Min, unsigned Max,

	// shift by 1 we get 0b0001 00100
	// shift by 1 we get 0b0001 0010

[DemandedBits] Support non-constant shift amounts #148880

Are you sure you want to change the base?

[DemandedBits] Support non-constant shift amounts #148880

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