Skip to content

[X86][FP16] Do not generate X86 FMIN/FMAX for FP16 when VLX not enabled #143100

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Jun 9, 2025
Merged

[X86][FP16] Do not generate X86 FMIN/FMAX for FP16 when VLX not enabled #143100

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
9 changes: 8 additions & 1 deletion llvm/lib/Target/X86/X86ISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -55357,10 +55357,17 @@ static SDValue combineFMinNumFMaxNum(SDNode *N, SelectionDAG &DAG,

const TargetLowering &TLI = DAG.getTargetLoweringInfo();

auto IsMinMaxLegal = [&](EVT VT) {
if (!TLI.isTypeLegal(VT))
return false;
return VT.getScalarType() != MVT::f16 ||
(Subtarget.hasFP16() && (VT == MVT::v32f16 || Subtarget.hasVLX()));
};
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

why not just widen (with zeros) to v32f16?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

There's a blocker issue. The general combiner always combines extract_subvector(insert_subvector(BinOP X, Y)) to BinOP X, Y. I created #143298 to show the problem.

OTOH, the AVX512FP16 w/o AVX512VL case doesn't occur in any real HW. We just need to make sure no crash here. Performance is not a concern.


if (!((Subtarget.hasSSE1() && VT == MVT::f32) ||
(Subtarget.hasSSE2() && VT == MVT::f64) ||
(Subtarget.hasFP16() && VT == MVT::f16) ||
(VT.isVector() && TLI.isTypeLegal(VT))))
(VT.isVector() && IsMinMaxLegal(VT))))
return SDValue();

SDValue Op0 = N->getOperand(0);
Expand Down
Loading
Loading