Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[RISCV] Rename operands used for branch and compressed jump targets. NFC #133364

Merged
merged 2 commits into from
Mar 28, 2025
Merged

[RISCV] Rename operands used for branch and compressed jump targets. NFC #133364

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
769e1c5
[RISCV] Rename operands used for branch and compressed jump targets. NFC
topperc Mar 28, 2025
fae9f5d
Merge remote-tracking branch 'origin/main' into pr/branch-jump
topperc Mar 28, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
16 changes: 4 additions & 12 deletions llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -842,8 +842,6 @@ struct RISCVOperand final : public MCParsedAsmOperand {

bool isUImm8Lsb000() const { return isUImmShifted<5, 3>(); }

bool isSImm9Lsb0() const { return isBareSimmNLsb0<9>(); }

bool isUImm9Lsb000() const { return isUImmShifted<6, 3>(); }

bool isUImm10Lsb00NonZero() const {
Expand Down Expand Up @@ -878,14 +876,10 @@ struct RISCVOperand final : public MCParsedAsmOperand {
VK == RISCVMCExpr::VK_TLSDESC_ADD_LO);
}

bool isSImm12Lsb0() const { return isBareSimmNLsb0<12>(); }

bool isSImm12Lsb00000() const {
return isSImmPred([](int64_t Imm) { return isShiftedInt<7, 5>(Imm); });
}

bool isSImm13Lsb0() const { return isBareSimmNLsb0<13>(); }

bool isSImm10Lsb0000NonZero() const {
return isSImmPred(
[](int64_t Imm) { return Imm != 0 && isShiftedInt<6, 4>(Imm); });
Expand Down Expand Up @@ -940,8 +934,6 @@ struct RISCVOperand final : public MCParsedAsmOperand {
VK == RISCVMCExpr::VK_TLSDESC_HI);
}

bool isSImm21Lsb0JAL() const { return isBareSimmNLsb0<21>(); }

bool isImmZero() const {
return isUImmPred([](int64_t Imm) { return 0 == Imm; });
}
Expand Down Expand Up @@ -1506,7 +1498,7 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
return generateImmOutOfRangeError(
Operands, ErrorInfo, 0, (1 << 8) - 8,
"immediate must be a multiple of 8 bytes in the range");
case Match_InvalidSImm9Lsb0:
case Match_InvalidBareSImm9Lsb0:
return generateImmOutOfRangeError(
Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2,
"immediate must be a multiple of 2 bytes in the range");
Expand Down Expand Up @@ -1536,15 +1528,15 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
Operands, ErrorInfo, -(1 << 11), (1 << 11) - 1,
"operand must be a symbol with %lo/%pcrel_lo/%tprel_lo specifier or an "
"integer in the range");
case Match_InvalidSImm12Lsb0:
case Match_InvalidBareSImm12Lsb0:
return generateImmOutOfRangeError(
Operands, ErrorInfo, -(1 << 11), (1 << 11) - 2,
"immediate must be a multiple of 2 bytes in the range");
case Match_InvalidSImm12Lsb00000:
return generateImmOutOfRangeError(
Operands, ErrorInfo, -(1 << 11), (1 << 11) - 32,
"immediate must be a multiple of 32 bytes in the range");
case Match_InvalidSImm13Lsb0:
case Match_InvalidBareSImm13Lsb0:
return generateImmOutOfRangeError(
Operands, ErrorInfo, -(1 << 12), (1 << 12) - 2,
"immediate must be a multiple of 2 bytes in the range");
Expand All @@ -1567,7 +1559,7 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
"%pcrel_hi/%got_pcrel_hi/%tls_ie_pcrel_hi/%tls_gd_pcrel_hi specifier "
"or "
"an integer in the range");
case Match_InvalidSImm21Lsb0JAL:
case Match_InvalidBareSImm21Lsb0:
return generateImmOutOfRangeError(
Operands, ErrorInfo, -(1 << 20), (1 << 20) - 2,
"immediate must be a multiple of 2 bytes in the range");
Expand Down
43 changes: 24 additions & 19 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -161,6 +161,11 @@ class UImmAsmOperand<int width, string suffix = "">
: ImmAsmOperand<"U", width, suffix> {
}

class BareSImmNLsb0AsmOperand<int width>
: ImmAsmOperand<"BareS", width, "Lsb0"> {
let PredicateMethod = "isBareSimmNLsb0<" # width # ">";
}

class RISCVOp<ValueType vt = XLenVT> : Operand<vt> {
let OperandNamespace = "RISCVOp";
}
Expand Down Expand Up @@ -271,8 +276,8 @@ def simm12_no6 : ImmLeaf<XLenVT, [{
return isInt<12>(Imm) && !isInt<6>(Imm) && isInt<12>(-Imm);}]>;

// A 13-bit signed immediate where the least significant bit is zero.
def simm13_lsb0 : Operand<OtherVT> {
let ParserMatchClass = SImmAsmOperand<13, "Lsb0">;
def bare_simm13_lsb0 : Operand<OtherVT> {
let ParserMatchClass = BareSImmNLsb0AsmOperand<13>;
let PrintMethod = "printBranchOperand";
let EncoderMethod = "getImmOpValueAsr1";
let DecoderMethod = "decodeSImmOperandAndLsl1<13>";
Expand Down Expand Up @@ -303,7 +308,7 @@ def uimm20_auipc : UImm20OperandMaybeSym {

def uimm20 : RISCVUImmOp<20>;

def Simm21Lsb0JALAsmOperand : SImmAsmOperand<21, "Lsb0JAL"> {
def Simm21Lsb0JALAsmOperand : BareSImmNLsb0AsmOperand<21> {
let ParserMethod = "parseJALOffset";
}

Expand Down Expand Up @@ -527,7 +532,7 @@ include "RISCVInstrFormatsV.td"

class BranchCC_rri<bits<3> funct3, string opcodestr>
: RVInstB<funct3, OPC_BRANCH, (outs),
(ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12),
(ins GPR:$rs1, GPR:$rs2, bare_simm13_lsb0:$imm12),
opcodestr, "$rs1, $rs2, $imm12">,
Sched<[WriteJmp, ReadJmp, ReadJmp]> {
let isBranch = 1;
Expand Down Expand Up @@ -959,30 +964,30 @@ def : InstAlias<"sgt $rd, $rs, $rt", (SLT GPR:$rd, GPR:$rt, GPR:$rs), 0>;
def : InstAlias<"sgtu $rd, $rs, $rt", (SLTU GPR:$rd, GPR:$rt, GPR:$rs), 0>;

def : InstAlias<"beqz $rs, $offset",
(BEQ GPR:$rs, X0, simm13_lsb0:$offset)>;
(BEQ GPR:$rs, X0, bare_simm13_lsb0:$offset)>;
def : InstAlias<"bnez $rs, $offset",
(BNE GPR:$rs, X0, simm13_lsb0:$offset)>;
(BNE GPR:$rs, X0, bare_simm13_lsb0:$offset)>;
def : InstAlias<"blez $rs, $offset",
(BGE X0, GPR:$rs, simm13_lsb0:$offset)>;
(BGE X0, GPR:$rs, bare_simm13_lsb0:$offset)>;
def : InstAlias<"bgez $rs, $offset",
(BGE GPR:$rs, X0, simm13_lsb0:$offset)>;
(BGE GPR:$rs, X0, bare_simm13_lsb0:$offset)>;
def : InstAlias<"bltz $rs, $offset",
(BLT GPR:$rs, X0, simm13_lsb0:$offset)>;
(BLT GPR:$rs, X0, bare_simm13_lsb0:$offset)>;
def : InstAlias<"bgtz $rs, $offset",
(BLT X0, GPR:$rs, simm13_lsb0:$offset)>;
(BLT X0, GPR:$rs, bare_simm13_lsb0:$offset)>;

// Always output the canonical mnemonic for the pseudo branch instructions.
// The GNU tools emit the canonical mnemonic for the branch pseudo instructions
// as well (e.g. "bgt" will be recognised by the assembler but never printed by
// objdump). Match this behaviour by setting a zero weight.
def : InstAlias<"bgt $rs, $rt, $offset",
(BLT GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>;
(BLT GPR:$rt, GPR:$rs, bare_simm13_lsb0:$offset), 0>;
def : InstAlias<"ble $rs, $rt, $offset",
(BGE GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>;
(BGE GPR:$rt, GPR:$rs, bare_simm13_lsb0:$offset), 0>;
def : InstAlias<"bgtu $rs, $rt, $offset",
(BLTU GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>;
(BLTU GPR:$rt, GPR:$rs, bare_simm13_lsb0:$offset), 0>;
def : InstAlias<"bleu $rs, $rt, $offset",
(BGEU GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>;
(BGEU GPR:$rt, GPR:$rs, bare_simm13_lsb0:$offset), 0>;

def : InstAlias<"j $offset", (JAL X0, simm21_lsb0_jal:$offset)>;
def : InstAlias<"jal $offset", (JAL X1, simm21_lsb0_jal:$offset)>;
Expand Down Expand Up @@ -1165,7 +1170,7 @@ def InsnI_Mem : DirectiveInsnI<(outs AnyReg:$rd), (ins uimm7_opcode:$opcode,
"$opcode, $funct3, $rd, ${imm12}(${rs1})">;
def InsnB : DirectiveInsnB<(outs), (ins uimm7_opcode:$opcode, uimm3:$funct3,
AnyReg:$rs1, AnyReg:$rs2,
simm13_lsb0:$imm12),
bare_simm13_lsb0:$imm12),
"$opcode, $funct3, $rs1, $rs2, $imm12">;
def InsnU : DirectiveInsnU<(outs AnyReg:$rd), (ins uimm7_opcode:$opcode,
uimm20_lui:$imm20),
Expand Down Expand Up @@ -1221,11 +1226,11 @@ def : InstAlias<".insn_i $opcode, $funct3, $rd, (${rs1})",
AnyReg:$rs1, 0)>;
def : InstAlias<".insn_b $opcode, $funct3, $rs1, $rs2, $imm12",
(InsnB uimm7_opcode:$opcode, uimm3:$funct3, AnyReg:$rs1,
AnyReg:$rs2, simm13_lsb0:$imm12)>;
AnyReg:$rs2, bare_simm13_lsb0:$imm12)>;
// Accept sb as an alias for b.
def : InstAlias<".insn_sb $opcode, $funct3, $rs1, $rs2, $imm12",
(InsnB uimm7_opcode:$opcode, uimm3:$funct3, AnyReg:$rs1,
AnyReg:$rs2, simm13_lsb0:$imm12)>;
AnyReg:$rs2, bare_simm13_lsb0:$imm12)>;
def : InstAlias<".insn_u $opcode, $rd, $imm20",
(InsnU AnyReg:$rd, uimm7_opcode:$opcode, uimm20_lui:$imm20)>;
def : InstAlias<".insn_j $opcode, $rd, $imm20",
Expand Down Expand Up @@ -1571,10 +1576,10 @@ let Predicates = [HasStdExtC, OptForMinSize] in {
// Match `riscv_brcc` and lower to the appropriate RISC-V branch instruction.
multiclass BccPat<CondCode Cond, RVInstB Inst> {
def : Pat<(riscv_brcc (XLenVT GPR:$rs1), GPR:$rs2, Cond, bb:$imm12),
(Inst GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12)>;
(Inst GPR:$rs1, GPR:$rs2, bare_simm13_lsb0:$imm12)>;
// Explicitly select 0 to X0. The register coalescer doesn't always do it.
def : Pat<(riscv_brcc (XLenVT GPR:$rs1), 0, Cond, bb:$imm12),
(Inst GPR:$rs1, (XLenVT X0), simm13_lsb0:$imm12)>;
(Inst GPR:$rs1, (XLenVT X0), bare_simm13_lsb0:$imm12)>;
}

class BrccCompressOpt<CondCode Cond, RVInstB Inst>
Expand Down
50 changes: 25 additions & 25 deletions llvm/lib/Target/RISCV/RISCVInstrInfoC.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -138,9 +138,9 @@ def uimm8_lsb000 : RISCVOp,
}

// A 9-bit signed immediate where the least significant bit is zero.
def simm9_lsb0 : Operand<OtherVT>,
ImmLeaf<XLenVT, [{return isShiftedInt<8, 1>(Imm);}]> {
let ParserMatchClass = SImmAsmOperand<9, "Lsb0">;
def bare_simm9_lsb0 : Operand<OtherVT>,
ImmLeaf<XLenVT, [{return isShiftedInt<8, 1>(Imm);}]> {
let ParserMatchClass = BareSImmNLsb0AsmOperand<9>;
let PrintMethod = "printBranchOperand";
let EncoderMethod = "getImmOpValueAsr1";
let DecoderMethod = "decodeSImmOperandAndLsl1<9>";
Expand Down Expand Up @@ -202,9 +202,9 @@ def simm10_lsb0000nonzero : RISCVOp,
}

// A 12-bit signed immediate where the least significant bit is zero.
def simm12_lsb0 : Operand<XLenVT>,
ImmLeaf<XLenVT, [{return isShiftedInt<11, 1>(Imm);}]> {
let ParserMatchClass = SImmAsmOperand<12, "Lsb0">;
def bare_simm12_lsb0 : Operand<OtherVT>,
ImmLeaf<XLenVT, [{return isShiftedInt<11, 1>(Imm);}]> {
let ParserMatchClass = BareSImmNLsb0AsmOperand<12>;
let PrintMethod = "printBranchOperand";
let EncoderMethod = "getImmOpValueAsr1";
let DecoderMethod = "decodeSImmOperandAndLsl1<12>";
Expand Down Expand Up @@ -258,7 +258,7 @@ class CStore_rri<bits<3> funct3, string OpcodeStr,

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class Bcz<bits<3> funct3, string OpcodeStr>
: RVInst16CB<funct3, 0b01, (outs), (ins GPRC:$rs1, simm9_lsb0:$imm),
: RVInst16CB<funct3, 0b01, (outs), (ins GPRC:$rs1, bare_simm9_lsb0:$imm),
OpcodeStr, "$rs1, $imm"> {
let isBranch = 1;
let isTerminator = 1;
Expand Down Expand Up @@ -417,7 +417,7 @@ def PseudoC_ADDI_NOP : Pseudo<(outs GPRX0:$rd), (ins GPRX0:$rs1, immzero:$imm),
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCall = 1,
DecoderNamespace = "RV32Only", Defs = [X1],
Predicates = [HasStdExtCOrZca, IsRV32] in
def C_JAL : RVInst16CJ<0b001, 0b01, (outs), (ins simm12_lsb0:$offset),
def C_JAL : RVInst16CJ<0b001, 0b01, (outs), (ins bare_simm12_lsb0:$offset),
"c.jal", "$offset">, Sched<[WriteJal]>;

let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
Expand Down Expand Up @@ -486,7 +486,7 @@ def C_ADDW : CA_ALU<0b100111, 0b01, "c.addw">,
}

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
def C_J : RVInst16CJ<0b101, 0b01, (outs), (ins simm12_lsb0:$offset),
def C_J : RVInst16CJ<0b101, 0b01, (outs), (ins bare_simm12_lsb0:$offset),
"c.j", "$offset">, Sched<[WriteJmp]> {
let isBranch = 1;
let isTerminator=1;
Expand Down Expand Up @@ -793,11 +793,11 @@ def InsnCA : DirectiveInsnCA<(outs AnyRegC:$rd), (ins uimm2_opcode:$opcode,
"$opcode, $funct6, $funct2, $rd, $rs2">;
def InsnCB : DirectiveInsnCB<(outs), (ins uimm2_opcode:$opcode, uimm3:$funct3,
AnyRegC:$rs1,
simm9_lsb0:$imm8),
bare_simm9_lsb0:$imm8),
"$opcode, $funct3, $rs1, $imm8">;
def InsnCJ : DirectiveInsnCJ<(outs), (ins uimm2_opcode:$opcode,
uimm3:$funct3,
simm12_lsb0:$imm11),
bare_simm12_lsb0:$imm11),
"$opcode, $funct3, $imm11">;
def Insn16 : RVInst16<(outs), (ins uimm16:$value), "", "", [], InstFormatOther> {
bits<16> value;
Expand Down Expand Up @@ -841,9 +841,9 @@ def : InstAlias<".insn_ca $opcode, $funct6, $funct2, $rd, $rs2",
uimm2:$funct2, AnyRegC:$rs2)>;
def : InstAlias<".insn_cb $opcode, $funct3, $rs1, $imm8",
(InsnCB uimm2_opcode:$opcode, uimm3:$funct3, AnyRegC:$rs1,
simm9_lsb0:$imm8)>;
bare_simm9_lsb0:$imm8)>;
def : InstAlias<".insn_cj $opcode, $funct3, $imm11",
(InsnCJ uimm2_opcode:$opcode, uimm3:$funct3, simm12_lsb0:$imm11)>;
(InsnCJ uimm2_opcode:$opcode, uimm3:$funct3, bare_simm12_lsb0:$imm11)>;
}

//===----------------------------------------------------------------------===/i
Expand Down Expand Up @@ -915,8 +915,8 @@ def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs1, simm6nonzero:$imm),
} // Predicates = [HasStdExtCOrZca]

let Predicates = [HasStdExtCOrZca, IsRV32] in {
def : CompressPat<(JAL X1, simm12_lsb0:$offset),
(C_JAL simm12_lsb0:$offset)>;
def : CompressPat<(JAL X1, bare_simm12_lsb0:$offset),
(C_JAL bare_simm12_lsb0:$offset)>;
} // Predicates = [HasStdExtCOrZca, IsRV32]

let Predicates = [HasStdExtCOrZca, IsRV64] in {
Expand Down Expand Up @@ -970,18 +970,18 @@ def : CompressPat<(ADDW GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
} // Predicates = [HasStdExtCOrZca, IsRV64]

let Predicates = [HasStdExtCOrZca] in {
def : CompressPat<(JAL X0, simm12_lsb0:$offset),
(C_J simm12_lsb0:$offset)>;
def : CompressPat<(BEQ GPRC:$rs1, X0, simm9_lsb0:$imm),
(C_BEQZ GPRC:$rs1, simm9_lsb0:$imm)>;
def : CompressPat<(JAL X0, bare_simm12_lsb0:$offset),
(C_J bare_simm12_lsb0:$offset)>;
def : CompressPat<(BEQ GPRC:$rs1, X0, bare_simm9_lsb0:$imm),
(C_BEQZ GPRC:$rs1, bare_simm9_lsb0:$imm)>;
let isCompressOnly = true in
def : CompressPat<(BEQ X0, GPRC:$rs1, simm9_lsb0:$imm),
(C_BEQZ GPRC:$rs1, simm9_lsb0:$imm)>;
def : CompressPat<(BNE GPRC:$rs1, X0, simm9_lsb0:$imm),
(C_BNEZ GPRC:$rs1, simm9_lsb0:$imm)>;
def : CompressPat<(BEQ X0, GPRC:$rs1, bare_simm9_lsb0:$imm),
(C_BEQZ GPRC:$rs1, bare_simm9_lsb0:$imm)>;
def : CompressPat<(BNE GPRC:$rs1, X0, bare_simm9_lsb0:$imm),
(C_BNEZ GPRC:$rs1, bare_simm9_lsb0:$imm)>;
let isCompressOnly = true in
def : CompressPat<(BNE X0, GPRC:$rs1, simm9_lsb0:$imm),
(C_BNEZ GPRC:$rs1, simm9_lsb0:$imm)>;
def : CompressPat<(BNE X0, GPRC:$rs1, bare_simm9_lsb0:$imm),
(C_BNEZ GPRC:$rs1, bare_simm9_lsb0:$imm)>;
} // Predicates = [HasStdExtCOrZca]

// Quadrant 2
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -590,10 +590,10 @@ let Predicates = [HasVendorXCVsimd, IsRV32] in {
let Predicates = [HasVendorXCVbi, IsRV32] in {
// Immediate branching operations
def CV_BEQIMM : CVInstImmBranch<0b110, (outs),
(ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
(ins GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12),
"cv.beqimm", "$rs1, $imm5, $imm12">, Sched<[]>;
def CV_BNEIMM : CVInstImmBranch<0b111, (outs),
(ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
(ins GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12),
"cv.bneimm", "$rs1, $imm5, $imm12">, Sched<[]>;
}

Expand Down Expand Up @@ -793,9 +793,9 @@ let Predicates = [HasVendorXCValu, IsRV32], AddedComplexity = 1 in {

let Predicates = [HasVendorXCVbi, IsRV32], AddedComplexity = 2 in {
def : Pat<(riscv_brcc GPR:$rs1, simm5:$imm5, SETEQ, bb:$imm12),
(CV_BEQIMM GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12)>;
(CV_BEQIMM GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12)>;
def : Pat<(riscv_brcc GPR:$rs1, simm5:$imm5, SETNE, bb:$imm12),
(CV_BNEIMM GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12)>;
(CV_BNEIMM GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12)>;

let usesCustomInserter = 1 in
def Select_GPR_Using_CC_Imm : Pseudo<(outs GPR:$dst),
Expand Down
5 changes: 3 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -314,7 +314,7 @@ class QCIRVInst16CI_RS1<bits<5> funct5, string OpcodeStr>

class QCIBranchInst_rii<bits<3> funct3, DAGOperand InTyImm5, string opcodestr>
: RVInstB<funct3, OPC_CUSTOM_3, (outs),
(ins GPRNoX0:$rs1, InTyImm5:$rs2, simm13_lsb0:$imm12),
(ins GPRNoX0:$rs1, InTyImm5:$rs2, bare_simm13_lsb0:$imm12),
opcodestr, "$rs1, $rs2, $imm12"> {
let isBranch = 1;
let isTerminator = 1;
Expand All @@ -324,7 +324,8 @@ class QCIBranchInst_rii<bits<3> funct3, DAGOperand InTyImm5, string opcodestr>
}

class QCIBranchInst48_rii<bits<5> funct5, DAGOperand InTyImm16, string opcodestr>
: RVInst48<(outs), (ins GPRNoX0:$rs1, InTyImm16:$imm16, simm13_lsb0:$imm12),
: RVInst48<(outs),
(ins GPRNoX0:$rs1, InTyImm16:$imm16, bare_simm13_lsb0:$imm12),
opcodestr, "$rs1, $imm16, $imm12", [], InstFormatOther> {
bits<5> rs1;
bits<16> imm16;
Expand Down