[VectorCombine] Failure to recognise vector splitting reduction pattern #239991

define i32 @src(<16 x i32> %w) {
  %l8 = shufflevector <16 x i32> %w, <16 x i32> %w, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  %h8 = shufflevector <16 x i32> %w, <16 x i32> %w, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  %s8 = add <8 x i32> %l8, %h8
  %l4 = shufflevector <8 x i32> %s8, <8 x i32> %s8, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %h4 = shufflevector <8 x i32> %s8, <8 x i32> %s8, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  %s4 = add <4 x i32> %l4, %h4
  %l2 = shufflevector <4 x i32> %s4, <4 x i32> %s4, <2 x i32> <i32 0, i32 1>
  %h2 = shufflevector <4 x i32> %s4, <4 x i32> %s4, <2 x i32> <i32 2, i32 3>
  %s2 = add <2 x i32> %l2, %h2
  %l1 = shufflevector <2 x i32> %s2, <2 x i32> %s2, <1 x i32> zeroinitializer
  %h1 = shufflevector <2 x i32> %s2, <2 x i32> %s2, <1 x i32> <i32 1>
  %s1 = add <1 x i32> %l1, %h1
  %r = extractelement <1 x i32> %s1, i64 0
  ret i32 %r
}

define i32 @tgt(<16 x i32> %w) {
  %r = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %w)
  ret i32 %r
}