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[LV][SLP][veclib] missed sin+cos/sincos vectorization without sincos veclib #239948
Description
https://godbolt.org/z/8erf85MTT
void foo(double *restrict a){
for(int i=0;i<8;i++){
a[i]=__builtin_sin(a[i])+__builtin_cos(a[i]);
}
}
void bar(double *restrict a){
for(int i=0;i<8;i++){
double s;
double c;
__builtin_sincos(a[i],&s,&c);
a[i]=s+c;
}
}
typedef double f64 [[clang::ext_vector_type(4)]];
f64 baz(f64 a){
return __builtin_elementwise_sin(a)+__builtin_elementwise_cos(a);
}-O3 -march=novalake -fveclib=libmvec -ffast-math (LV) or with -fno-unroll-loops (SLP)
foo:
pushp rbx
sub rsp, 144
mov rbx, rdi
vmovsd xmm0, qword ptr [rdi + 32]
lea rdi, [rsp + 72]
lea rsi, [rsp + 64]
call sincos@PLT
vmovsd xmm0, qword ptr [rbx + 40]
lea rdi, [rsp + 56]
lea rsi, [rsp + 48]
call sincos@PLT
vmovsd xmm0, qword ptr [rbx + 48]
lea rdi, [rsp + 40]
lea rsi, [rsp + 32]
call sincos@PLT
vmovsd xmm0, qword ptr [rbx + 56]
lea rdi, [rsp + 24]
lea rsi, [rsp + 16]
call sincos@PLT
vmovsd xmm0, qword ptr [rbx]
vmovsd xmm1, qword ptr [rbx + 8]
vmovsd qword ptr [rsp + 8], xmm1
lea rdi, [rsp + 136]
lea rsi, [rsp + 128]
call sincos@PLT
lea rdi, [rsp + 120]
lea rsi, [rsp + 112]
vmovsd xmm0, qword ptr [rsp + 8]
call sincos@PLT
vmovsd xmm0, qword ptr [rbx + 16]
lea rdi, [rsp + 104]
lea rsi, [rsp + 96]
call sincos@PLT
vmovsd xmm0, qword ptr [rbx + 24]
lea rdi, [rsp + 88]
lea rsi, [rsp + 80]
call sincos@PLT
vmovsd xmm0, qword ptr [rsp + 64]
vmovhpd xmm0, xmm0, qword ptr [rsp + 48]
vmovsd xmm1, qword ptr [rsp + 32]
vmovhpd xmm1, xmm1, qword ptr [rsp + 16]
vmovsd xmm2, qword ptr [rsp + 128]
vmovhpd xmm2, xmm2, qword ptr [rsp + 112]
vinsertf128 ymm0, ymm0, xmm1, 1
vmovsd xmm1, qword ptr [rsp + 96]
vmovhpd xmm1, xmm1, qword ptr [rsp + 80]
vinsertf128 ymm1, ymm2, xmm1, 1
vinsertf64x4 zmm0, zmm1, ymm0, 1
vmovsd xmm1, qword ptr [rsp + 72]
vmovhpd xmm1, xmm1, qword ptr [rsp + 56]
vmovsd xmm2, qword ptr [rsp + 40]
vmovhpd xmm2, xmm2, qword ptr [rsp + 24]
vmovsd xmm3, qword ptr [rsp + 136]
vmovhpd xmm3, xmm3, qword ptr [rsp + 120]
vmovsd xmm4, qword ptr [rsp + 104]
vmovhpd xmm4, xmm4, qword ptr [rsp + 88]
vinsertf128 ymm1, ymm1, xmm2, 1
vinsertf128 ymm2, ymm3, xmm4, 1
vinsertf64x4 zmm1, zmm2, ymm1, 1
vaddpd zmm0, zmm1, zmm0
vmovupd zmmword ptr [rbx], zmm0
add rsp, 144
popp rbx
vzeroupper
ret
bar:
pushp rbx
sub rsp, 144
mov rbx, rdi
vmovsd xmm0, qword ptr [rdi + 32]
lea rdi, [rsp + 72]
lea rsi, [rsp + 64]
call sincos@PLT
vmovsd xmm0, qword ptr [rbx + 40]
lea rdi, [rsp + 56]
lea rsi, [rsp + 48]
call sincos@PLT
vmovsd xmm0, qword ptr [rbx + 48]
lea rdi, [rsp + 40]
lea rsi, [rsp + 32]
call sincos@PLT
vmovsd xmm0, qword ptr [rbx + 56]
lea rdi, [rsp + 24]
lea rsi, [rsp + 16]
call sincos@PLT
vmovsd xmm0, qword ptr [rbx]
vmovsd xmm1, qword ptr [rbx + 8]
vmovsd qword ptr [rsp + 8], xmm1
lea rdi, [rsp + 136]
lea rsi, [rsp + 128]
call sincos@PLT
lea rdi, [rsp + 120]
lea rsi, [rsp + 112]
vmovsd xmm0, qword ptr [rsp + 8]
call sincos@PLT
vmovsd xmm0, qword ptr [rbx + 16]
lea rdi, [rsp + 104]
lea rsi, [rsp + 96]
call sincos@PLT
vmovsd xmm0, qword ptr [rbx + 24]
lea rdi, [rsp + 88]
lea rsi, [rsp + 80]
call sincos@PLT
vmovsd xmm0, qword ptr [rsp + 64]
vmovhpd xmm0, xmm0, qword ptr [rsp + 48]
vmovsd xmm1, qword ptr [rsp + 32]
vmovhpd xmm1, xmm1, qword ptr [rsp + 16]
vmovsd xmm2, qword ptr [rsp + 128]
vmovhpd xmm2, xmm2, qword ptr [rsp + 112]
vinsertf128 ymm0, ymm0, xmm1, 1
vmovsd xmm1, qword ptr [rsp + 96]
vmovhpd xmm1, xmm1, qword ptr [rsp + 80]
vinsertf128 ymm1, ymm2, xmm1, 1
vinsertf64x4 zmm0, zmm1, ymm0, 1
vmovsd xmm1, qword ptr [rsp + 72]
vmovhpd xmm1, xmm1, qword ptr [rsp + 56]
vmovsd xmm2, qword ptr [rsp + 40]
vmovhpd xmm2, xmm2, qword ptr [rsp + 24]
vmovsd xmm3, qword ptr [rsp + 136]
vmovhpd xmm3, xmm3, qword ptr [rsp + 120]
vmovsd xmm4, qword ptr [rsp + 104]
vmovhpd xmm4, xmm4, qword ptr [rsp + 88]
vinsertf128 ymm1, ymm1, xmm2, 1
vinsertf128 ymm2, ymm3, xmm4, 1
vinsertf64x4 zmm1, zmm2, ymm1, 1
vaddpd zmm0, zmm1, zmm0
vmovupd zmmword ptr [rbx], zmm0
add rsp, 144
popp rbx
vzeroupper
ret
baz:
sub rsp, 72
vmovups ymmword ptr [rsp], ymm0
call _ZGVdN4v_sin@PLT
vmovups ymmword ptr [rsp + 32], ymm0
vmovupd ymm0, ymmword ptr [rsp]
call _ZGVdN4v_cos@PLT
vaddpd ymm0, ymm0, ymmword ptr [rsp + 32]
add rsp, 72
retSince #194616, InstCombine folds sin+cos into sincos, and #194639 splits vector sincos into vector sin + cos when sincos veclib is not available, but LV/SLP is unaware of this. so even if vectorization is actually possible, LV/SLP fails to vectorize.
cc @kito-cheng
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