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1 change: 1 addition & 0 deletions meson.build
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Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@ project('debugcc',

platforms = [
'ipq8064',
'milos',
'msm8936',
'msm8994',
'msm8996',
Expand Down
349 changes: 349 additions & 0 deletions milos.c
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Original file line number Diff line number Diff line change
@@ -0,0 +1,349 @@
// SPDX-License-Identifier: BSD-3-Clause
/* Copyright (c) 2025, Luca Weiss */

#include <sys/mman.h>
#include <err.h>
#include <fcntl.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>

#include "debugcc.h"

static struct gcc_mux gcc = {
.mux = {
.phys = 0x100000,
.size = 0x1f4200,

.measure = measure_gcc,

.enable_reg = 0x62004,
.enable_mask = BIT(0),

.mux_reg = 0x62024,
.mux_mask = 0x3ff,

.div_reg = 0x62000,
.div_mask = 0xf,
.div_val = 2,
},

.xo_div4_reg = 0x62008,
.debug_ctl_reg = 0x62048,
.debug_status_reg = 0x6204c,
};

static struct debug_mux cam_cc = {
.phys = 0xadb0000,
.size = 0x40000,
.block_name = "cam",

.measure = measure_leaf,
.parent = &gcc.mux,
.parent_mux_val = 0x87,

.enable_reg = 0x26008,
.enable_mask = BIT(0),

.mux_reg = 0x30128,
.mux_mask = 0xff,

.div_reg = 0x26004,
.div_mask = 0xf,
.div_val = 2,
};

static struct debug_mux disp_cc = {
.phys = 0xaf00000,
.size = 0x20000,
.block_name = "disp",

.measure = measure_leaf,
.parent = &gcc.mux,
.parent_mux_val = 0x8c,

.enable_reg = 0xd004,
.enable_mask = BIT(0),

.mux_reg = 0x11000,
.mux_mask = 0x1ff,

.div_reg = 0xd000,
.div_mask = 0xf,
.div_val = 4,
};

static struct debug_mux gpu_cc = {
.phys = 0x3d90000,
.size = 0xa000,
.block_name = "gpu",

.measure = measure_leaf,
.parent = &gcc.mux,
.parent_mux_val = 0x187,

.enable_reg = 0x9274,
.enable_mask = BIT(0),

.mux_reg = 0x9564,
.mux_mask = 0xff,

.div_reg = 0x9270,
.div_mask = 0xf,
.div_val = 2,
};

static struct debug_mux video_cc = {
.phys = 0xaaf0000,
.size = 0x10000,
.block_name = "video",

.measure = measure_leaf,
.parent = &gcc.mux,
.parent_mux_val = 0x95,

.enable_reg = 0x80fc,
.enable_mask = BIT(0),

.mux_reg = 0x9a4c,
.mux_mask = 0x3f,

.div_reg = 0x80f8,
.div_mask = 0xf,
.div_val = 3,
};

static struct measure_clk milos_clocks[] = {
/* GCC entries */
{ "gcc_aggre_noc_pcie_axi_clk", &gcc.mux, 0x4d },
{ "gcc_aggre_ufs_phy_axi_clk", &gcc.mux, 0x4f },
{ "gcc_aggre_usb3_prim_axi_clk", &gcc.mux, 0x4e },
{ "gcc_boot_rom_ahb_clk", &gcc.mux, 0xe9 },
{ "gcc_camera_hf_axi_clk", &gcc.mux, 0x83 },
{ "gcc_camera_sf_axi_clk", &gcc.mux, 0x84 },
{ "gcc_cfg_noc_pcie_anoc_ahb_clk", &gcc.mux, 0x39 },
{ "gcc_cfg_noc_usb3_prim_axi_clk", &gcc.mux, 0x20 },
{ "gcc_cnoc_pcie_sf_axi_clk", &gcc.mux, 0x19 },
{ "gcc_ddrss_gpu_axi_clk", &gcc.mux, 0x105 },
{ "gcc_ddrss_pcie_sf_qtb_clk", &gcc.mux, 0x106 },
{ "gcc_disp_gpll0_div_clk_src", &gcc.mux, 0x8d },
{ "gcc_disp_hf_axi_clk", &gcc.mux, 0x8a },
{ "gcc_gp1_clk", &gcc.mux, 0x148 },
{ "gcc_gp2_clk", &gcc.mux, 0x149 },
{ "gcc_gp3_clk", &gcc.mux, 0x14a },
{ "gcc_gpu_gpll0_clk_src", &gcc.mux, 0x18b },
{ "gcc_gpu_gpll0_div_clk_src", &gcc.mux, 0x18c },
{ "gcc_gpu_memnoc_gfx_clk", &gcc.mux, 0x188 },
{ "gcc_gpu_snoc_dvm_gfx_clk", &gcc.mux, 0x18a },
{ "gcc_pcie_0_aux_clk", &gcc.mux, 0x150 },
{ "gcc_pcie_0_cfg_ahb_clk", &gcc.mux, 0x14f },
{ "gcc_pcie_0_mstr_axi_clk", &gcc.mux, 0x14e },
{ "gcc_pcie_0_phy_rchng_clk", &gcc.mux, 0x152 },
{ "gcc_pcie_0_pipe_clk", &gcc.mux, 0x151 },
{ "gcc_pcie_0_pipe_div2_clk", &gcc.mux, 0x153 },
{ "gcc_pcie_0_slv_axi_clk", &gcc.mux, 0x14d },
{ "gcc_pcie_0_slv_q2a_axi_clk", &gcc.mux, 0x14c },
{ "gcc_pcie_1_aux_clk", &gcc.mux, 0x1b7 },
{ "gcc_pcie_1_cfg_ahb_clk", &gcc.mux, 0x1b6 },
{ "gcc_pcie_1_mstr_axi_clk", &gcc.mux, 0x1b5 },
{ "gcc_pcie_1_phy_rchng_clk", &gcc.mux, 0x1b9 },
{ "gcc_pcie_1_pipe_clk", &gcc.mux, 0x1b8 },
{ "gcc_pcie_1_pipe_div2_clk", &gcc.mux, 0x1ba },
{ "gcc_pcie_1_slv_axi_clk", &gcc.mux, 0x1b4 },
{ "gcc_pcie_1_slv_q2a_axi_clk", &gcc.mux, 0x1b3 },
{ "gcc_pcie_rscc_cfg_ahb_clk", &gcc.mux, 0x1a0 },
{ "gcc_pcie_rscc_xo_clk", &gcc.mux, 0x1a1 },
{ "gcc_pdm2_clk", &gcc.mux, 0xda },
{ "gcc_pdm_ahb_clk", &gcc.mux, 0xd8 },
{ "gcc_pdm_xo4_clk", &gcc.mux, 0xd9 },
{ "gcc_qmip_camera_nrt_ahb_clk", &gcc.mux, 0x81 },
{ "gcc_qmip_camera_rt_ahb_clk", &gcc.mux, 0x82 },
{ "gcc_qmip_disp_ahb_clk", &gcc.mux, 0x89 },
{ "gcc_qmip_gpu_ahb_clk", &gcc.mux, 0x185 },
{ "gcc_qmip_pcie_ahb_clk", &gcc.mux, 0x14b },
{ "gcc_qmip_video_cv_cpu_ahb_clk", &gcc.mux, 0x92 },
{ "gcc_qmip_video_cvp_ahb_clk", &gcc.mux, 0x8f },
{ "gcc_qmip_video_v_cpu_ahb_clk", &gcc.mux, 0x91 },
{ "gcc_qmip_video_vcodec_ahb_clk", &gcc.mux, 0x90 },
{ "gcc_qupv3_wrap0_core_2x_clk", &gcc.mux, 0xc3 },
{ "gcc_qupv3_wrap0_core_clk", &gcc.mux, 0xc2 },
{ "gcc_qupv3_wrap0_qspi_ref_clk", &gcc.mux, 0xcb },
{ "gcc_qupv3_wrap0_s0_clk", &gcc.mux, 0xc4 },
{ "gcc_qupv3_wrap0_s1_clk", &gcc.mux, 0xc5 },
{ "gcc_qupv3_wrap0_s2_clk", &gcc.mux, 0xc6 },
{ "gcc_qupv3_wrap0_s3_clk", &gcc.mux, 0xc7 },
{ "gcc_qupv3_wrap0_s4_clk", &gcc.mux, 0xc8 },
{ "gcc_qupv3_wrap0_s5_clk", &gcc.mux, 0xc9 },
{ "gcc_qupv3_wrap0_s6_clk", &gcc.mux, 0xca },
{ "gcc_qupv3_wrap1_core_2x_clk", &gcc.mux, 0xcf },
{ "gcc_qupv3_wrap1_core_clk", &gcc.mux, 0xce },
{ "gcc_qupv3_wrap1_qspi_ref_clk", &gcc.mux, 0xd7 },
{ "gcc_qupv3_wrap1_s0_clk", &gcc.mux, 0xd0 },
{ "gcc_qupv3_wrap1_s1_clk", &gcc.mux, 0xd1 },
{ "gcc_qupv3_wrap1_s2_clk", &gcc.mux, 0xd2 },
{ "gcc_qupv3_wrap1_s3_clk", &gcc.mux, 0xd3 },
{ "gcc_qupv3_wrap1_s4_clk", &gcc.mux, 0xd4 },
{ "gcc_qupv3_wrap1_s5_clk", &gcc.mux, 0xd5 },
{ "gcc_qupv3_wrap1_s6_clk", &gcc.mux, 0xd6 },
{ "gcc_qupv3_wrap_0_m_ahb_clk", &gcc.mux, 0xc0 },
{ "gcc_qupv3_wrap_0_s_ahb_clk", &gcc.mux, 0xc1 },
{ "gcc_qupv3_wrap_1_m_ahb_clk", &gcc.mux, 0xcc },
{ "gcc_qupv3_wrap_1_s_ahb_clk", &gcc.mux, 0xcd },
{ "gcc_sdcc1_ahb_clk", &gcc.mux, 0x1af },
{ "gcc_sdcc1_apps_clk", &gcc.mux, 0x1b0 },
{ "gcc_sdcc1_ice_core_clk", &gcc.mux, 0x1b1 },
{ "gcc_sdcc2_ahb_clk", &gcc.mux, 0xbe },
{ "gcc_sdcc2_apps_clk", &gcc.mux, 0xbd },
{ "gcc_ufs_phy_ahb_clk", &gcc.mux, 0x157 },
{ "gcc_ufs_phy_axi_clk", &gcc.mux, 0x156 },
{ "gcc_ufs_phy_ice_core_clk", &gcc.mux, 0x15d },
{ "gcc_ufs_phy_phy_aux_clk", &gcc.mux, 0x15e },
{ "gcc_ufs_phy_rx_symbol_0_clk", &gcc.mux, 0x159 },
{ "gcc_ufs_phy_rx_symbol_1_clk", &gcc.mux, 0x15f },
{ "gcc_ufs_phy_tx_symbol_0_clk", &gcc.mux, 0x158 },
{ "gcc_ufs_phy_unipro_core_clk", &gcc.mux, 0x15c },
{ "gcc_usb30_prim_atb_clk", &gcc.mux, 0xb8 },
{ "gcc_usb30_prim_master_clk", &gcc.mux, 0xaf },
{ "gcc_usb30_prim_mock_utmi_clk", &gcc.mux, 0xb1 },
{ "gcc_usb30_prim_sleep_clk", &gcc.mux, 0xb0 },
{ "gcc_usb3_prim_phy_aux_clk", &gcc.mux, 0xb2 },
{ "gcc_usb3_prim_phy_com_aux_clk", &gcc.mux, 0xb3 },
{ "gcc_usb3_prim_phy_pipe_clk", &gcc.mux, 0xb4 },
{ "gcc_video_axi0_clk", &gcc.mux, 0x93 },
{ "mc_cc_debug_mux", &gcc.mux, 0x112 },
{ "measure_only_cnoc_clk", &gcc.mux, 0x17 },
{ "measure_only_gcc_camera_ahb_clk", &gcc.mux, 0x80 },
{ "measure_only_gcc_camera_hf_xo_clk", &gcc.mux, 0x85 },
{ "measure_only_gcc_camera_sf_xo_clk", &gcc.mux, 0x86 },
{ "measure_only_gcc_disp_ahb_clk", &gcc.mux, 0x88 },
{ "measure_only_gcc_disp_xo_clk", &gcc.mux, 0x8b },
{ "measure_only_gcc_gpu_cfg_ahb_clk", &gcc.mux, 0x184 },
{ "measure_only_gcc_video_ahb_clk", &gcc.mux, 0x8e },
{ "measure_only_gcc_video_xo_clk", &gcc.mux, 0x94 },
{ "measure_only_ipa_2x_clk", &gcc.mux, 0x170 },
{ "measure_only_memnoc_clk", &gcc.mux, 0x10a },
{ "measure_only_pcie_0_pipe_clk", &gcc.mux, 0x154 },
{ "measure_only_pcie_1_pipe_clk", &gcc.mux, 0x1bb },
{ "measure_only_snoc_clk", &gcc.mux, 0xb },
{ "measure_only_ufs_phy_rx_symbol_0_clk", &gcc.mux, 0x15b },
{ "measure_only_ufs_phy_rx_symbol_1_clk", &gcc.mux, 0x161 },
{ "measure_only_ufs_phy_tx_symbol_0_clk", &gcc.mux, 0x15a },
{ "measure_only_usb3_phy_wrapper_gcc_usb30_pipe_clk", &gcc.mux, 0xb9 },
/* CAMCC Entries */
{ "cam_cc_bps_ahb_clk", &cam_cc, 0x12 },
{ "cam_cc_bps_areg_clk", &cam_cc, 0x11 },
{ "cam_cc_bps_clk", &cam_cc, 0xe },
{ "cam_cc_camnoc_atb_clk", &cam_cc, 0x3e },
{ "cam_cc_camnoc_axi_hf_clk", &cam_cc, 0x39 },
{ "cam_cc_camnoc_axi_sf_clk", &cam_cc, 0x38 },
{ "cam_cc_camnoc_nrt_axi_clk", &cam_cc, 0x3f },
{ "cam_cc_camnoc_rt_axi_clk", &cam_cc, 0x3c },
{ "cam_cc_cci_0_clk", &cam_cc, 0x35 },
{ "cam_cc_cci_1_clk", &cam_cc, 0x36 },
{ "cam_cc_core_ahb_clk", &cam_cc, 0x42 },
{ "cam_cc_cpas_ahb_clk", &cam_cc, 0x37 },
{ "cam_cc_cre_ahb_clk", &cam_cc, 0x47 },
{ "cam_cc_cre_clk", &cam_cc, 0x46 },
{ "cam_cc_csi0phytimer_clk", &cam_cc, 0x6 },
{ "cam_cc_csi1phytimer_clk", &cam_cc, 0x8 },
{ "cam_cc_csi2phytimer_clk", &cam_cc, 0xa },
{ "cam_cc_csi3phytimer_clk", &cam_cc, 0xc },
{ "cam_cc_csiphy0_clk", &cam_cc, 0x7 },
{ "cam_cc_csiphy1_clk", &cam_cc, 0x9 },
{ "cam_cc_csiphy2_clk", &cam_cc, 0xb },
{ "cam_cc_csiphy3_clk", &cam_cc, 0xd },
{ "cam_cc_icp_atb_clk", &cam_cc, 0x2e },
{ "cam_cc_icp_clk", &cam_cc, 0x32 },
{ "cam_cc_icp_cti_clk", &cam_cc, 0x2f },
{ "cam_cc_icp_ts_clk", &cam_cc, 0x30 },
{ "cam_cc_mclk0_clk", &cam_cc, 0x1 },
{ "cam_cc_mclk1_clk", &cam_cc, 0x2 },
{ "cam_cc_mclk2_clk", &cam_cc, 0x3 },
{ "cam_cc_mclk3_clk", &cam_cc, 0x4 },
{ "cam_cc_mclk4_clk", &cam_cc, 0x5 },
{ "cam_cc_ope_0_ahb_clk", &cam_cc, 0x17 },
{ "cam_cc_ope_0_areg_clk", &cam_cc, 0x16 },
{ "cam_cc_ope_0_clk", &cam_cc, 0x13 },
{ "cam_cc_soc_ahb_clk", &cam_cc, 0x41 },
{ "cam_cc_sys_tmr_clk", &cam_cc, 0x34 },
{ "cam_cc_tfe_0_ahb_clk", &cam_cc, 0x1f },
{ "cam_cc_tfe_0_clk", &cam_cc, 0x18 },
{ "cam_cc_tfe_0_cphy_rx_clk", &cam_cc, 0x1e },
{ "cam_cc_tfe_0_csid_clk", &cam_cc, 0x1b },
{ "cam_cc_tfe_1_ahb_clk", &cam_cc, 0x26 },
{ "cam_cc_tfe_1_clk", &cam_cc, 0x20 },
{ "cam_cc_tfe_1_cphy_rx_clk", &cam_cc, 0x25 },
{ "cam_cc_tfe_1_csid_clk", &cam_cc, 0x23 },
{ "cam_cc_tfe_2_ahb_clk", &cam_cc, 0x2d },
{ "cam_cc_tfe_2_clk", &cam_cc, 0x27 },
{ "cam_cc_tfe_2_cphy_rx_clk", &cam_cc, 0x2c },
{ "cam_cc_tfe_2_csid_clk", &cam_cc, 0x2a },
{ "cam_cc_top_shift_clk", &cam_cc, 0x44 },
{ "measure_only_cam_cc_gdsc_clk", &cam_cc, 0x43 },
{ "measure_only_cam_cc_sleep_clk", &cam_cc, 0x45 },
/* DISPCC Entries */
{ "disp_cc_mdss_accu_clk", &disp_cc, 0x70 },
{ "disp_cc_mdss_ahb1_clk", &disp_cc, 0x5d },
{ "disp_cc_mdss_ahb_clk", &disp_cc, 0x5a },
{ "disp_cc_mdss_byte0_clk", &disp_cc, 0x24 },
{ "disp_cc_mdss_byte0_intf_clk", &disp_cc, 0x25 },
{ "disp_cc_mdss_dptx0_aux_clk", &disp_cc, 0x51 },
{ "disp_cc_mdss_dptx0_crypto_clk", &disp_cc, 0x33 },
{ "disp_cc_mdss_dptx0_link_clk", &disp_cc, 0x30 },
{ "disp_cc_mdss_dptx0_link_intf_clk", &disp_cc, 0x32 },
{ "disp_cc_mdss_dptx0_pixel0_clk", &disp_cc, 0x3c },
{ "disp_cc_mdss_dptx0_pixel1_clk", &disp_cc, 0x3d },
{ "disp_cc_mdss_dptx0_usb_router_link_intf_clk", &disp_cc, 0x31 },
{ "disp_cc_mdss_esc0_clk", &disp_cc, 0x17 },
{ "disp_cc_mdss_mdp1_clk", &disp_cc, 0x5b },
{ "disp_cc_mdss_mdp_clk", &disp_cc, 0x58 },
{ "disp_cc_mdss_mdp_lut1_clk", &disp_cc, 0x5c },
{ "disp_cc_mdss_mdp_lut_clk", &disp_cc, 0x59 },
{ "disp_cc_mdss_non_gdsc_ahb_clk", &disp_cc, 0x5e },
{ "disp_cc_mdss_pclk0_clk", &disp_cc, 0x20 },
{ "disp_cc_mdss_rscc_ahb_clk", &disp_cc, 0x5f },
{ "disp_cc_mdss_rscc_vsync_clk", &disp_cc, 0x56 },
{ "disp_cc_mdss_vsync1_clk", &disp_cc, 0x55 },
{ "disp_cc_mdss_vsync_clk", &disp_cc, 0x50 },
{ "measure_only_disp_cc_sleep_clk", &disp_cc, 0x67 },
{ "measure_only_disp_cc_xo_clk", &disp_cc, 0x57 },
/* GPUCC entries */
{ "gpu_cc_ahb_clk", &gpu_cc, 0x17 },
{ "gpu_cc_cx_accu_shift_clk", &gpu_cc, 0x24 },
{ "gpu_cc_cx_ff_clk", &gpu_cc, 0x20 },
{ "gpu_cc_cx_gmu_clk", &gpu_cc, 0x1d },
{ "gpu_cc_cxo_clk", &gpu_cc, 0x1e },
{ "gpu_cc_dpm_clk", &gpu_cc, 0x25 },
{ "gpu_cc_freq_measure_clk", &gpu_cc, 0xf },
{ "gpu_cc_gx_accu_shift_clk", &gpu_cc, 0x15 },
{ "gpu_cc_gx_acd_ahb_ff_clk", &gpu_cc, 0x13 },
{ "gpu_cc_gx_gmu_clk", &gpu_cc, 0x11 },
{ "gpu_cc_gx_rcg_ahb_ff_clk", &gpu_cc, 0x14 },
{ "gpu_cc_hub_aon_clk", &gpu_cc, 0x2a },
{ "gpu_cc_hub_cx_int_clk", &gpu_cc, 0x1f },
{ "gpu_cc_memnoc_gfx_clk", &gpu_cc, 0x21 },
{ "gx_clkctl_debug_mux", &gpu_cc, 0xb },
{ "measure_only_gpu_cc_cb_clk", &gpu_cc, 0x28 },
{ "measure_only_gpu_cc_cxo_aon_clk", &gpu_cc, 0xe },
{ "measure_only_gpu_cc_demet_clk", &gpu_cc, 0x10 },
{ "measure_only_gpu_cc_gx_ahb_ff_clk", &gpu_cc, 0x12 },
{ "measure_only_gpu_cc_rscc_hub_aon_clk", &gpu_cc, 0x29 },
{ "measure_only_gpu_cc_rscc_xo_aon_clk", &gpu_cc, 0xd },
{ "measure_only_gpu_cc_sleep_clk", &gpu_cc, 0x1b },
/* VIDEOCC Entries */
{ "measure_only_video_cc_ahb_clk", &video_cc, 0x5 },
{ "measure_only_video_cc_sleep_clk", &video_cc, 0x9 },
{ "measure_only_video_cc_xo_clk", &video_cc, 0x6 },
{ "video_cc_mvs0_clk", &video_cc, 0x3 },
{ "video_cc_mvs0_shift_clk", &video_cc, 0x7 },
{ "video_cc_mvs0c_clk", &video_cc, 0x1 },
{ "video_cc_mvs0c_shift_clk", &video_cc, 0x8 },
{}
};

struct debugcc_platform milos_debugcc = {
"milos",
milos_clocks,
};