TPU.sv is a tensor processing unit coded in SystemVerilog based on Google's first-generation TPU. It is a generic and resource-adjustable machine learning inference accelerator for educational purposes. TPU.sv is thought for deployment as a co-processor alongside a general-purpose CPU.

Project Structure

• apps/
  Software applications and demo programs

• docs/
  Project documentation, specifications, and images

• fpga/
  Helper files for FPGA deployment

• hdl/
  Hardware description of TPU.sv

  • hdl/lib/ - Libraries for common parameters, functions, tasks, etc.
  • hdl/rtl/ - RTL description of TPU.sv
  • hdl/sim/ - Testbenches

• sdk/
  Software development kit for TPU.sv

Architectural Overview

Credits

The following sources have been primarily referenced for this project:

• Google's 2018 paper introducing TPU's architecture
• "Implementierung einer Tensor Processing Unit" by Jonas Fuhrmann
• tinyTPU by Jonas Fuhrmann

Status

• ✅ SDK implemented (2025-06-19)
• ✅ AXI wrapper implemented and tested (2025-06-10)
• ✅ Core complete and simulation passing (2024-10-12)

Next Steps

• 🚧 Evaluation on real hardware with actual machine learning workloads
• 🚧 Refinement of the hardware description
• 🚧 Enhancement of the documentation

Contributing

Contributions of any kind are welcome. If you encounter a bug, please do not hesitate to create an issue.

License

TPU.sv is licensed under the MIT License. See LICENSE for details.

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