New rule needed for signal declration using records to initialize.

[ungultig1]

Environment
Windows 11, newest vsg

Describe the bug
similar to the constant_400 rule, there must be also a rule for the signal declration assigning record and a default value:

Recap constant_400 rule:

Violation

constant c_default_values : t_address_en := (
  c_address_control => false,
  c_address_data => true,
  others => false
);

Fix

constant c_default_values : t_address_en := (
  c_address_control => false,
  c_address_data     => true,
  others                   => false
);

To Reproduce
Steps to reproduce the behavior with singal assigning record:

Violation

signal mySignal  : t_address_en := (
  c_address_control => false,
  c_address_data => true,
  others => false
);

Fix

constant mySignal  : t_address_en := (
  c_address_control => false,
  c_address_data     => true,
  others                   => false
);

Expected behavior
Expected behaviour as rule constant_400, also considering correct format behaviour for comments inside the declreation, as well as the open/close scopes.

Screenshots
Outcome atm:

Expecting:

Thank you.

Ps.: could you also explain the tox.ini?
Exectuing this, and build the project, is it the same behaviour as installing with "setup.py" prior? it confused me..

[JHertz5]

Hi @ungultig1

similar to the constant_400 rule, there must be also a rule for the signal declration assigning record and a default value:

Thanks for raising this issue. I can take a look at putting a branch together for the new rule.
Just to check, your code snippets seem to have a mistake in the "violation" examples - constant_400 and the new signal rule should align the assignment operators =>, but in your examples, they are not aligned. I'm guessing that is an accident? Otherwise, I'd need some more info on what informs the indentation levels to understand what you want out of this rule.

also considering correct format behaviour for comments inside the declreation, as well as the open/close scopes.

You also mention handling of comments inside aggregate assignment. This as far as I'm aware is not something that the constant_400 does well either currently. Unless constant_400 matches the behaviour that you want with comments, I suggest that you open a separate issue to specify what you're looking for, as it is a completely independent task to adding a new rules for signal declarations and will make it easier to manage the work.

Ps.: could you also explain the tox.ini? Exectuing this, and build the project, is it the same behaviour as installing with "setup.py" prior? it confused me..

I wasn't involved in putting the tox.ini file together, but from what little I know - the tox.ini file is kind of like a makefile but focussed on testing. It defines the procedures that are following for the various unit tests, build tests, style tests, etc. that for this repository's regression test suite. I don't think that it's the same as running setup.py, but as part of those tests, tox runs builds packages of the tool for different versions of python.
As I mentioned, I don't know much about it, I'd wait for @jeremiah-c-leary to get a proper answer on,

[JHertz5]

Hi @ungultig1. I've raised a PR, #1505, which I hope will resolve your issue. When you have a chance, please give it a try and let me know whether it works as you'd expect. The new rule is called signal_401.

Note that I had to use this config to disable rules that conflict with the new rule to avoid getting errors.

rule:
  signal_007:
    disable: true
  element_association_100:
    disable: true

[ungultig1]

Hi @JHertz5 ,

thank you for solving the problem.
It does the allingning now, thank you.

But unfortunately, the following wont work as expected:

1. The operator ":= " is not behind the singal declration
2. the indent won't be applied.
3. The parentheses ( ... ) is not formatted as expected
4. As well as the closing ");".

Atm:

Expecting:

[JHertz5]

Hi @ungultig1. Ah ok, I understand now, your request is not limited only to the functionality of constant_400. I'll need to produce a few more rules to achieve what you want. I'll let you know when I've had a chance to make further changes.

[ungultig1]

Hi @JHertz5 ,

were you successful in including the checks?

Thank you.

[JHertz5]

Hey @ungultig1, I haven't had a chance to work on this yet. There are a few new rules required, so there is likely a fair bit of work involved. I'll try to work on it this week, but I can't make any promises as I'm doing this in my spare time. As I mentioned above, I'll let you know when I've had a chance to make further changes.

[JHertz5]

FYI @ungultig1, I'm starting to look at these now. I'll keep you updated as I make progress.

Regarding your code examples, it is much more useful if you paste them as plaintext code blocks rather than images. You can change plaintext to a code block surrounding it with triple backticks "``". See this link for more details.

```vhdl
  my_sig <= my_var;
```

becomes

  my_sig <= my_var;

Doing this will make it possible for me to copy your code examples into my code editor and use them in my testing.

[JHertz5]

I've added rule signal_018 to the PR, which should enforce the := assignment operator being on the same line as the previous token. The other rules are a bit more complex to implement because they conflict with signal_400. I'll try to make some progress soon, but I'll need to modify signal_400 in a way that is quite difficult.

[JHertz5]

An update on the above - I've managed to find a good solution to the problem with signal_400. @ungultig1 I'll try to finalise the changes this weekend, and when that's done I'll ask you to check the branch again.

[JHertz5]

@ungultig1 I believe that the branch is now producing your expected result. Please give it a try when you have a chance and let me know whether you feel that the branch is ready to be merged. Here's the test that I've done on my side.

Input:

architecture rtl of test is

  signal wr_r : xec_wr
:= (
                slv2_p_start_RO_synced => (others => '0'),
                slv4_wr_en_to_mem      => (others => '0'),
                sl_wr_en_left          => '0',
                sl_wr_en_right         => '0'
);

begin

end architecture rtl;

Config:

rule:
  signal_007:
    disable: true

Output:

architecture rtl of test is

  signal wr_r : xec_wr :=
  (
    slv2_p_start_RO_synced => (others => '0'),
    slv4_wr_en_to_mem      => (others => '0'),
    sl_wr_en_left          => '0',
    sl_wr_en_right         => '0'
  );

begin

end architecture rtl;