Environment
Ubuntu 22.04
Python 3.13.2
vsg 3.31.0

Describe the bug
The ports in the entity and component declarations are checked using the naming rules port_011 or port_025. Only the ports in the entity declaration should be checked, as the port naming in the component declaration must match the declaration in the VHDL entity or Verilog module it describes.

To Reproduce
Check the following code snippet with either rule port_011 or port_025 enabled.

library ieee;
use ieee.std_logic_1164.all;

entity a is
  port (
    clk_i : in  std_logic;
    d_i   : in  std_logic;
    q_o   : out std_logic
  );
end entity a;

architecture structure of a is

  component b is
    port (
      c  : in  std_logic;
      d  : in  std_logic;
      q  : out std_logic
    );
  end component b;

begin

  u0: component b
    port map (
      c => clk_i,
      d => d_i,
      q => q_o
  );

end architecture structure;

Expected behavior
Port naming in component declaration must be ignored, because the naming of the ports is declared elsewhere.