x86: Add initial support for EMR

Add platform check and initial support for EMR. Signed-off-by: Tinghao Zhang <[email protected]>
intel · Dec 26, 2023 · d3fcffc · d3fcffc
1 parent 564a4d4
commit d3fcffc
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Showing 4 changed files with 39 additions and 1 deletion.
diff --git a/x86/include/skl.h b/x86/include/skl.h
@@ -51,6 +51,10 @@ extern void spr_profiling_config(perf_count_id_t, struct _plat_event_config *);
 extern void spr_ll_config(struct _plat_event_config *);
 extern int spr_offcore_num(void);
 
+extern void emr_profiling_config(perf_count_id_t, struct _plat_event_config *);
+extern void emr_ll_config(struct _plat_event_config *);
+extern int emr_offcore_num(void);
+
 #ifdef __cplusplus
 }
 #endif

diff --git a/x86/include/types.h b/x86/include/types.h
@@ -47,12 +47,13 @@ typedef enum {
 	CPU_SKX,
 	CPU_ICX,
 	CPU_SPR,
+	CPU_EMR,
 	CPU_ZEN,
 	CPU_ZEN3,
 	CPU_ZEN4
 } cpu_type_t;
 
-#define	CPU_TYPE_NUM	15
+#define	CPU_TYPE_NUM	16
 
 typedef enum {
 	PERF_COUNT_INVALID = -1,

diff --git a/x86/plat.c b/x86/plat.c
@@ -52,6 +52,7 @@ s_plat_profiling_config[CPU_TYPE_NUM] = {
 	skl_profiling_config,
 	icx_profiling_config,
 	spr_profiling_config,
+	emr_profiling_config,
 	zen_profiling_config,
 	zen3_profiling_config,
 	zen4_profiling_config
@@ -71,6 +72,7 @@ s_plat_ll_config[CPU_TYPE_NUM] = {
 	skl_ll_config,
 	icx_ll_config,
 	spr_ll_config,
+	emr_ll_config,
 	zen_ll_config,
 	zen_ll_config,
 	zen_ll_config
@@ -90,6 +92,7 @@ s_plat_offcore_num[CPU_TYPE_NUM] = {
 	skl_offcore_num,
 	icx_offcore_num,
 	spr_offcore_num,
+	emr_offcore_num,
 	zen_offcore_num,
 	zen_offcore_num,
 	zen_offcore_num
@@ -193,6 +196,9 @@ cpu_type_get(void)
 		case 143:
                         type = CPU_SPR;
 			break;
+		case 207:
+                        type = CPU_EMR;
+			break;
 		}
 	} else if (family == 23) {	/* Family 17h */
 		type = CPU_ZEN;
@@ -243,6 +249,7 @@ plat_detect(void)
 	case CPU_SKX:
 	case CPU_ICX:
 	case CPU_SPR:
+	case CPU_EMR:
 	case CPU_ZEN:
 	case CPU_ZEN3:
 	case CPU_ZEN4:

diff --git a/x86/skl.c b/x86/skl.c
@@ -63,6 +63,14 @@ static plat_event_config_t s_spr_config[PERF_COUNT_NUM] = {
 	{ PERF_TYPE_RAW, 0x012B, 0x53, 0x104000001, 0, 0, "off_core_response_1" }
 };
 
+static plat_event_config_t s_emr_config[PERF_COUNT_NUM] = {
+	{ PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, 0x53, 0, "cpu_clk_unhalted.core" },
+	{ PERF_TYPE_RAW, 0x012A, 0x53, 0x730000001, "off_core_response_0" },
+	{ PERF_TYPE_HARDWARE, PERF_COUNT_HW_REF_CPU_CYCLES, 0x53, 0, "cpu_clk_unhalted.ref" },
+	{ PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, 0x53, 0, "instr_retired.any" },
+	{ PERF_TYPE_RAW, 0x012B, 0x53, 0x104000001, "off_core_response_1" }
+};
+
 static plat_event_config_t s_skl_ll = {
 	PERF_TYPE_RAW, 0x01CD, 0x53, LL_THRESH, 0, 1, "mem_trans_retired.latency_above_threshold"
 };
@@ -85,6 +93,12 @@ spr_profiling_config(perf_count_id_t perf_count_id, plat_event_config_t *cfg)
 	plat_config_get(perf_count_id, cfg, s_spr_config);
 }
 
+void
+emr_profiling_config(perf_count_id_t perf_count_id, plat_event_config_t *cfg)
+{
+	plat_config_get(perf_count_id, cfg, s_emr_config);
+}
+
 void
 skl_ll_config(plat_event_config_t *cfg)
 {
@@ -103,6 +117,12 @@ spr_ll_config(plat_event_config_t *cfg)
 	skl_ll_config(cfg);
 }
 
+void
+emr_ll_config(plat_event_config_t *cfg)
+{
+	skl_ll_config(cfg);
+}
+
 int
 skl_offcore_num(void)
 {
@@ -120,3 +140,9 @@ spr_offcore_num(void)
 {
 	return skl_offcore_num();
 }
+
+int
+emr_offcore_num(void)
+{
+	return skl_offcore_num();
+}