[XPU][OptRed] Define triton_intel_gpu.simd_reduce and use in optimized transposed reduction
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victor-eds
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Something is off with the vISA generated. I'm looking into that. Delay reviews. |
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IGC vISA parser fails to parse this when combined with DPAS instruction. Waiting for fix. |
etiotto
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Jan 29, 2025
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| // RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm | FileCheck %s | |||
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[nit]: -split-input-file isn't required
| // To get the asm code: | ||
| // builder.dump() | ||
| // ``` | ||
| // To get all the `mlir::Value` used in the VISA code, |
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| // To get all the `mlir::Value` used in the VISA code, | |
| // To get all the `mlir::Value` used in the VISA code: |
| Operand *newListOperand() { return newOperand(); } | ||
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| Operand *newListOperand(ArrayRef<std::pair<mlir::Value, std::string>> items) { | ||
| auto *list = newOperand(); |
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| auto *list = newOperand(); | |
| Operand *list = newOperand(); |
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| for (auto &item : items) { | ||
| list->listAppend(newOperand(item.first, item.second)); |
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| for (auto &item : items) { | |
| list->listAppend(newOperand(item.first, item.second)); | |
| for (auto &[val, constraint] : items) { | |
| list->listAppend(newOperand(val, constraint)); |
| } | ||
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| Operand *listGet(size_t nth) const { | ||
| assert(nth < list.size()); |
| [&](std::unique_ptr<Operand> &a, std::unique_ptr<Operand> &b) { | ||
| auto ida = std::find(order.begin(), order.end(), a.get()); | ||
| auto idb = std::find(order.begin(), order.end(), b.get()); | ||
| assert(ida != order.end()); |
| #include "mlir/Transforms/DialectConversion.h" | ||
| #include "triton/Conversion/TritonGPUToLLVM/AsmFormat.h" | ||
| #include "llvm/Support/raw_ostream.h" | ||
| // TODO(Superjomn): unify to llvm::raw_string_ostream |
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| VISABuilder::Operand *VISABuilder::newOperand(StringRef constraint, bool init) { | ||
| // Constraint should be something like "=rw" | ||
| assert(constraint[0] == '='); |
| VISABuilder::Operand *VISABuilder::newOperand(StringRef constraint, bool init) { | ||
| // Constraint should be something like "=rw" | ||
| assert(constraint[0] == '='); | ||
| auto *opr = newOperand(); |
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| auto *opr = newOperand(); | |
| Operand *opr = newOperand(); |
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| VISABuilder::Operand *VISABuilder::newOperand(unsigned operandIndex) { | ||
| assert(operandIndex < oprCounter && "operand index out of range"); | ||
| auto *opr = newOperand(); |
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| auto *opr = newOperand(); | |
| Operand *opr = newOperand(); |
PietroGhg
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…zed transposed reduction Define SIMD transpose-reduce operation performing a SIMD reduction while transposing the implicit SIMD matrix. See description definition for further context. Using this operation in the transpose reduction pass allows us to perform the optimization while not using SLM. Signed-off-by: victor-eds <[email protected]> Co-authored-by: chengjunlu <[email protected]> Signed-off-by: Victor Perez <[email protected]>
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As discussed in our offline architecture mtg @chengjunlu will review this PR and determine whether this implementation is still needed or can be super seeded by the his approach. |
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Define SIMD transpose-reduce operation performing a SIMD reduction while transposing the implicit SIMD matrix. See description definition for further context.
Using this operation in the transpose reduction pass allows us to perform the optimization while not using SLM.