Mips-cpu-verilog-version

5 stage pipeline with BHT(branch history table)

set main.v as top file

make sure u can add the dist_mem_gen to generate the memmory.

u can also write a module to replace the dist_mem_gen(not suggest)

there are some coe file which u can take them to test the cpu

Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
test_code		test_code
Alu.v		Alu.v
AluSrc_mux.v		AluSrc_mux.v
EX_MEM.v		EX_MEM.v
ID_EX.v		ID_EX.v
IF_ID.v		IF_ID.v
MEM_WB.v		MEM_WB.v
README.md		README.md
branch_decoder.v		branch_decoder.v
control_unit.v		control_unit.v
dst_mux.v		dst_mux.v
main.v		main.v
mutex2_width32.v		mutex2_width32.v
reg.v		reg.v
regfile.v		regfile.v
shownum.v		shownum.v

Provide feedback