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cmd/internal/obj/riscv: add support for Zihintpause extension on riscv64 #75616

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cmd/internal/obj/riscv: add support for Zihintpause extension on riscv64 #75616

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cmd/internal/obj/riscv: add support for Zihintpause extension on riscv64
lxq015 Sep 26, 2025
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lxq015 Sep 26, 2025
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lxq015 Sep 26, 2025
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3 changes: 3 additions & 0 deletions src/cmd/asm/internal/asm/testdata/riscv64.s
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Original file line number Diff line number Diff line change
Expand Up @@ -195,6 +195,9 @@ start:
RDTIME X5 // f32210c0
RDINSTRET X5 // f32220c0

// 10.1: Zihintpause Extension for Pause Hint
PAUSE // 0f000001

// 12.3: Integer Conditional Operations (Zicond)
CZEROEQZ X5, X6, X7 // b353530e
CZEROEQZ X5, X7 // b3d3530e
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1 change: 1 addition & 0 deletions src/cmd/internal/obj/riscv/anames.go
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1 change: 1 addition & 0 deletions src/cmd/internal/obj/riscv/cpu.go
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Expand Up @@ -1504,6 +1504,7 @@ const (
ANEG
ANEGW
ANOT
APAUSE
ARDCYCLE
ARDINSTRET
ARDTIME
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4 changes: 4 additions & 0 deletions src/cmd/internal/obj/riscv/obj.go
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Expand Up @@ -3732,6 +3732,10 @@ func instructionsForProg(p *obj.Prog) []*instruction {
}
ins.imm = -1

case APAUSE:
ins.as, ins.rd, ins.rs1, ins.rs2 = AFENCE, REG_ZERO, REG_ZERO, obj.REG_NONE
ins.imm = 0x010

case ASEQZ:
// SEQZ rs, rd -> SLTIU $1, rs, rd
ins.as = ASLTIU
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