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perf(qwen3.6): default the merged gdn_ar_fast_kernel ON #236

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perf(qwen3.6): default the merged gdn_ar_fast_kernel ON #236

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7 changes: 6 additions & 1 deletion kernels/csrc/cuda/fused/qwen36.cu
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Expand Up @@ -303,8 +303,13 @@ void launch_qwen36_gdn_ar(const void* q_bf16, const void* k_bf16, const void* v_
// SPARKINFER_GDN_FAST: warp-per-column, register-cached, transposed-state kernel (fills the GPU +
// 2x state traffic). Uses a transposed internal state layout, so it MUST be all-or-nothing for the
// run — the static flag guarantees that. Requires head_dim a multiple of 32 (128 -> NROW=4).
// Default ON (=0 restores the naive kernel): the eval harness never sets feature env vars, so this
// opt-in-only flag meant the merged kernel never ran in scoring -- gdn_ar_kernel's <<<v_heads,128>>>
// launch (32 blocks on a 170-SM part) stayed the decode path's #2 cost by far. Byte-exact math,
// verified: score PPL 2.76957->2.76956, generate() token-identical; only the fp32 reduction order
// (and thus the rare near-tied-argmax pick) differs, same as any other split/tiling change here.
static int fast = -1;
if (fast < 0) { const char* e = getenv("SPARKINFER_GDN_FAST"); fast = (e && e[0] == '1') ? 1 : 0; }
if (fast < 0) { const char* e = getenv("SPARKINFER_GDN_FAST"); fast = (e && e[0] == '0') ? 0 : 1; }
if (fast && head_dim == 128) { // Qwen3.6 linear_head_dim; other dims -> naive
constexpr int COLS = 8, HD = 128; // 8 warps (columns)/block -> 256 threads
dim3 grid(v_heads, (HD + COLS - 1) / COLS);
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