Use pCUDA for a supported subset to support any GPU via AdaptiveCpp#1
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fodinabor wants to merge 13 commits into
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Use pCUDA for a supported subset to support any GPU via AdaptiveCpp#1fodinabor wants to merge 13 commits into
fodinabor wants to merge 13 commits into
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…tion Replace assertion with fallback to default compute capability (sm_75) when nvidia-smi is unavailable. This allows lit tests to run in environments without GPU tools installed.
Add HCF (Heterogeneous Container Format) support for kernel metadata: - New hcf_adapter module with kernel metadata generation utilities - HCFMetadata class for collecting and serializing kernel information - Kernel launch wrapper generation for pCUDA runtime - LLVM IR argument extraction for parameter canonicalization Integrates with AdaptiveCpp's kernel cache infrastructure: - Support for multi-backend targeting (NVIDIA PTX, AMD AMDGPU, SPIR-V, Host) - Device property metadata (warp size, max threads, shared memory) - Foundation for runtime JIT compilation and kernel specialization - Enables research evaluation of MimIR vs AdaptiveCpp approaches PCUDAHostEmitter enhanced to track kernel metadata via hcf_metadata_ member. All tests remain passing (227/246, no regressions).
Replace NVIDIA-specific intrinsics with AdaptiveCpp SSCP builtins: - Use __acpp_sscp_get_group_id/get_local_id instead of llvm.nvvm.* - Use __acpp_sscp_jit_reflect_warp_size instead of llvm.nvvm.read.ptx.sreg - Use generic llvm.convergent.barrier instead of llvm.nvvm.barrier0 - Remove spir_kernel attribute, use generic void function This enables the pCUDA backend to generate LLVM IR compatible with AdaptiveCpp's SSCP (Single-pass SYCL C++ compiler) pipeline, which can be lowered to any backend (NVIDIA PTX, AMD AMDGPU, Intel SPIR-V, etc.) in stage 2 compilation. The generated LLVM IR will now work with: - AdaptiveCpp's llvm-to-amdgpu translator (for AMD GPUs) - AdaptiveCpp's llvm-to-ptx translator (for NVIDIA GPUs) - AdaptiveCpp's llvm-to-spirv translator (for Intel/other GPUs)
Enable --device-target pcuda flag in MimIR compiler: - Add 'pcuda' as valid device target option (alongside 'none' and 'nvptx') - Wire pCUDA device target to ll-host-pcuda and ll-dev-pcuda backends - Update help text to show all available device targets - Fix double 'void' typo in pCUDA device emitter Now users can compile with --device-target pcuda to use SSCP-compatible pCUDA backends instead of NVPTX. Example: ./build/bin/mim kernel.mim --device-target pcuda --ll-device-only -o device.ll This generates generic LLVM IR that can be compiled by AdaptiveCpp for multiple GPU backends (NVIDIA PTX, AMD AMDGPU, Intel SPIR-V, etc.)
…ckend - Introduced `set_hcf_embed` method in `PCUDAHostEmitter` to handle HCF blob and object ID. - Implemented `emit_hcf_embedding` to generate LLVM IR constants and runtime externs for HCF registration. - Updated `PCUDADeviceEmitter` to emit kernel metadata and handle shared memory and symbol pointers. - Added `emit_host_with_embedded_device` function to manage the generation of device LLVM IR, linking, and embedding into the host output. - Registered new backend `ll-host-pcuda-embed-dev` in the NVPTX plugin to facilitate the new embedding functionality.
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Just a very rough (Claude-supported) port of this branch to use pCUDA instead of plain CUDA - i.e. generate device LLVM IR in the SSCP dialect (opposed to NVPTX) and use p-prefixed runtime calls.
This will then go through AdaptiveCpp's JIT infrastructure to target any AdaptiveCpp-supported devices (i.e. AMD, Nvidia, Intel, Metal GPUs, OpenCL devices, ..).
Mostly want this PR opened for it to live somewhere and show the feasibility.
There are certain restrictions: AdaptiveCpp doesn't actually support constant/global/texture memory atm, for example.
I also haven't wrapped the shuffle-like intrinsics (using SYCL's sub-group semantics, which are very similar to warp intrinsics.)