move index out of signal type

ekiwi · Jun 13, 2024 · caf740b · caf740b
1 parent f96c38d
commit caf740b
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Showing 4 changed files with 19 additions and 20 deletions.
diff --git a/Cargo.toml b/Cargo.toml
@@ -8,7 +8,7 @@ members = ["wellen"]
 default-members = ["wellen"]
 
 [workspace.package]
-version = "0.9.11"
+version = "0.9.12"
 edition = "2021"
 # we require the `div_ceil` method on integers
 rust-version = "1.73.0"

diff --git a/wellen/src/fst.rs b/wellen/src/fst.rs
@@ -179,7 +179,7 @@ impl SignalWriter {
                         self.time_indices.push(time_idx);
                     }
                 }
-                SignalType::BitVector(len, _) => {
+                SignalType::BitVector(len) => {
                     let bits = len.get();
 
                     // nvc will declare boolean signals as 1-bit bit-vectors and then generate
@@ -288,7 +288,7 @@ impl SignalWriter {
                     self.data_bytes,
                 )
             }
-            SignalType::BitVector(len, _) => {
+            SignalType::BitVector(len) => {
                 debug_assert!(self.strings.is_empty());
                 let (bytes, meta_byte) = get_len_and_meta(self.max_states, len.get());
                 let encoding = SignalEncoding::BitVector {

diff --git a/wellen/src/hierarchy.rs b/wellen/src/hierarchy.rs
@@ -250,15 +250,15 @@ impl SignalRef {
 pub enum SignalType {
     String,
     Real,
-    BitVector(NonZeroU32, Option<VarIndex>),
+    BitVector(NonZeroU32),
 }
 
 impl SignalType {
-    pub fn from_uint(len: u32, index: Option<VarIndex>) -> Self {
+    pub fn from_uint(len: u32) -> Self {
         match NonZeroU32::new(len) {
             // a zero length signal should be represented as a 1-bit signal
-            None => SignalType::BitVector(NonZeroU32::new(1).unwrap(), index),
-            Some(value) => SignalType::BitVector(value, index),
+            None => SignalType::BitVector(NonZeroU32::new(1).unwrap()),
+            Some(value) => SignalType::BitVector(value),
         }
     }
 }
@@ -270,6 +270,7 @@ pub struct Var {
     var_tpe: VarType,
     direction: VarDirection,
     signal_tpe: SignalType,
+    index: Option<VarIndex>,
     signal_idx: SignalRef,
     enum_type: Option<EnumTypeId>,
     vhdl_type_name: Option<HierarchyStringId>,
@@ -329,10 +330,7 @@ impl Var {
         self.direction
     }
     pub fn index(&self) -> Option<VarIndex> {
-        match &self.signal_tpe {
-            SignalType::BitVector(_, index) => *index,
-            _ => None,
-        }
+        self.index
     }
     pub fn signal_ref(&self) -> SignalRef {
         self.signal_idx
@@ -341,7 +339,7 @@ impl Var {
         match &self.signal_tpe {
             SignalType::String => None,
             SignalType::Real => None,
-            SignalType::BitVector(len, _) => Some(len.get()),
+            SignalType::BitVector(len) => Some(len.get()),
         }
     }
     pub fn is_real(&self) -> bool {
@@ -351,7 +349,7 @@ impl Var {
         matches!(self.signal_tpe, SignalType::String)
     }
     pub fn is_bit_vector(&self) -> bool {
-        matches!(self.signal_tpe, SignalType::BitVector(_, _))
+        matches!(self.signal_tpe, SignalType::BitVector(_))
     }
     pub fn is_1bit(&self) -> bool {
         match self.length() {
@@ -1081,14 +1079,15 @@ impl HierarchyBuilder {
         let signal_tpe = match tpe {
             VarType::String => SignalType::String,
             VarType::Real => SignalType::Real,
-            _ => SignalType::from_uint(raw_length, index),
+            _ => SignalType::from_uint(raw_length),
         };
 
         // now we can build the node data structure and store it
         let node = Var {
             parent,
             name,
             var_tpe: tpe,
+            index,
             direction,
             signal_tpe,
             signal_idx,
@@ -1185,8 +1184,8 @@ mod tests {
         // unfortunately this one is pretty big
         assert_eq!(std::mem::size_of::<HierarchyItemId>(), 8);
 
-        // 4 byte length, 8 byte index + tag + padding
-        assert_eq!(std::mem::size_of::<SignalType>(), 16);
+        // 4 byte length + tag + padding
+        assert_eq!(std::mem::size_of::<SignalType>(), 8);
 
         // Var
         assert_eq!(

diff --git a/wellen/src/wavemem.rs b/wellen/src/wavemem.rs
@@ -151,7 +151,7 @@ impl Reader {
                         &mut strings,
                     );
                 }
-                SignalType::BitVector(signal_len, _) => {
+                SignalType::BitVector(signal_len) => {
                     load_fixed_len_signal(
                         &mut data.as_ref(),
                         time_idx_offset,
@@ -178,7 +178,7 @@ impl Reader {
                 debug_assert!(data_bytes.is_empty());
                 Signal::new_var_len(id, time_indices, strings)
             }
-            SignalType::BitVector(len, _) => {
+            SignalType::BitVector(len) => {
                 debug_assert!(strings.is_empty());
                 let (bytes, meta_byte) = get_len_and_meta(meta.max_states, len.get());
                 let encoding = SignalEncoding::BitVector {
@@ -707,7 +707,7 @@ impl SignalEncoder {
         let time_idx_delta = time_index - self.prev_time_idx;
         self.max_states = States::join(self.max_states, states);
         match self.tpe {
-            SignalType::BitVector(len, _) => {
+            SignalType::BitVector(len) => {
                 let bits = len.get();
                 if bits == 1 {
                     debug_assert_eq!(value.len(), 1);
@@ -771,7 +771,7 @@ impl SignalEncoder {
     fn add_vcd_change(&mut self, time_index: u16, value: &[u8]) {
         let time_idx_delta = time_index - self.prev_time_idx;
         match self.tpe {
-            SignalType::BitVector(len, _) => {
+            SignalType::BitVector(len) => {
                 let value_bits: &[u8] = match value[0] {
                     b'b' | b'B' => &value[1..],
                     _ => value,