fix issue_34

litex/caravel_platform.py

@@ -192,7 +192,6 @@ def _new_print_combinatorial_logic_sim(f, ns):
     verilog._print_combinatorial_logic_sim = _new_print_combinatorial_logic_sim
 
     def _new_print_module(f, ios, name, ns, attr_translate):
-        sigs = verilog.list_signals(f) | verilog.list_special_ios(f, ins=True, outs=True, inouts=True)
         special_outs = verilog.list_special_ios(f, ins=False, outs=True, inouts=True)
         inouts = verilog.list_special_ios(f, ins=False, outs=False, inouts=True)
         targets = verilog.list_targets(f) | special_outs
@@ -226,6 +225,15 @@ def _new_print_module(f, ios, name, ns, attr_translate):
                 sig.direction = "input"
                 r += "\tinput wire " + verilog._print_signal(ns, sig)
         r += "\n);\n\n"
+        return r
+
+    verilog._print_module = _new_print_module
+
+    def _new_print_signals(f, ios, name, ns, attr_translate):
+        sigs = verilog.list_signals(f) | verilog.list_special_ios(f, ins=True, outs=True, inouts=True)
+        special_outs = verilog.list_special_ios(f, ins=False, outs=True, inouts=True)
+        wires = verilog._list_comb_wires(f) | special_outs
+        r = ""
         for sig in sorted(sigs - ios, key=lambda x: x.duid):
             attr = verilog._print_attribute(sig.attr, attr_translate)
             if attr:
@@ -237,4 +245,4 @@ def _new_print_module(f, ios, name, ns, attr_translate):
         r += "\n"
         return r
 
-    verilog._print_module = _new_print_module
+    verilog._print_signals = _new_print_signals

litex/requirements.txt

@@ -11,3 +11,4 @@ git+https://github.com/enjoy-digital/liteeth
 git+https://github.com/enjoy-digital/liteiclink
 git+https://github.com/enjoy-digital/litescope
 git+https://github.com/litex-hub/pythondata-misc-tapcfg.git
+git+https://github.com/litex-hub/pythondata-software-compiler_rt.git