zynq_axi_ddr_barebone

minimal code to access ps DDR from PL. generate incremental data in PL and write it to ps DDR address 0x00400000 via s_AXI_HP0 port,

use key[0] to reset axi write module, can be removed. use key[1] to reset axi write data, can be removed

create ps block design according to axi_ddrpdf, view ddr memory at 0x00400000 in SDK to check whether data is correct.

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
README.md		README.md
axi_ddr.pdf		axi_ddr.pdf
axi_ddr_wrapper.v		axi_ddr_wrapper.v
axi_hp0_wr.v		axi_hp0_wr.v
fifo_generator_0_stub.vhdl		fifo_generator_0_stub.vhdl

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