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lines changed Original file line number Diff line number Diff line change @@ -804,15 +804,15 @@ void verilog_typecheckt::collect_symbols(
804804 {
805805 auto ¶meter_decl = to_verilog_parameter_decl (module_item);
806806 collect_symbols (parameter_decl.type ());
807- for (auto &decl : parameter_decl.declarations ())
808- collect_symbols (parameter_decl.type (), decl );
807+ for (auto &declarator : parameter_decl.declarators ())
808+ collect_symbols (parameter_decl.type (), declarator );
809809 }
810810 else if (module_item.id () == ID_local_parameter_decl)
811811 {
812812 auto &localparam_decl = to_verilog_local_parameter_decl (module_item);
813813 collect_symbols (localparam_decl.type ());
814- for (auto &decl : localparam_decl.declarations ())
815- collect_symbols (localparam_decl.type (), decl );
814+ for (auto &declarator : localparam_decl.declarators ())
815+ collect_symbols (localparam_decl.type (), declarator );
816816 }
817817 else if (module_item.id () == ID_decl)
818818 {
Original file line number Diff line number Diff line change @@ -146,19 +146,19 @@ static void dependencies_rec(
146146 else if (module_item.id () == ID_parameter_decl)
147147 {
148148 auto ¶meter_decl = to_verilog_parameter_decl (module_item);
149- for (auto &decl : parameter_decl.declarations ())
149+ for (auto &declarator : parameter_decl.declarators ())
150150 {
151- dependencies_rec (decl .type (), dest);
152- dependencies_rec (decl .value (), dest);
151+ dependencies_rec (declarator .type (), dest);
152+ dependencies_rec (declarator .value (), dest);
153153 }
154154 }
155155 else if (module_item.id () == ID_local_parameter_decl)
156156 {
157157 auto &localparam_decl = to_verilog_local_parameter_decl (module_item);
158- for (auto &decl : localparam_decl.declarations ())
158+ for (auto &declarator : localparam_decl.declarators ())
159159 {
160- dependencies_rec (decl .type (), dest);
161- dependencies_rec (decl .value (), dest);
160+ dependencies_rec (declarator .type (), dest);
161+ dependencies_rec (declarator .value (), dest);
162162 }
163163 }
164164 else if (module_item.id () == ID_decl)
Original file line number Diff line number Diff line change @@ -680,6 +680,7 @@ class verilog_declaratort : public exprt
680680
681681using verilog_declaratorst = std::vector<verilog_declaratort>;
682682
683+ // / a SystemVerilog parameter declaration
683684class verilog_parameter_declt : public verilog_module_itemt
684685{
685686public:
@@ -690,12 +691,12 @@ class verilog_parameter_declt : public verilog_module_itemt
690691 using declaratort = verilog_declaratort;
691692 using declaratorst = verilog_declaratorst;
692693
693- const declaratorst &declarations () const
694+ const declaratorst &declarators () const
694695 {
695696 return (const declaratorst &)operands ();
696697 }
697698
698- declaratorst &declarations ()
699+ declaratorst &declarators ()
699700 {
700701 return (declaratorst &)operands ();
701702 }
@@ -725,12 +726,12 @@ class verilog_local_parameter_declt : public verilog_module_itemt
725726 using declaratort = verilog_declaratort;
726727 using declaratorst = verilog_declaratorst;
727728
728- const declaratorst &declarations () const
729+ const declaratorst &declarators () const
729730 {
730731 return (const declaratorst &)operands ();
731732 }
732733
733- declaratorst &declarations ()
734+ declaratorst &declarators ()
734735 {
735736 return (declaratorst &)operands ();
736737 }
Original file line number Diff line number Diff line change @@ -43,8 +43,8 @@ verilog_typecheckt::get_parameter_declarators(
4343
4444 for (auto &item : module_items)
4545 if (item.id () == ID_parameter_decl)
46- for (auto &decl : to_verilog_parameter_decl (item).declarations ())
47- declarators.push_back (decl );
46+ for (auto &declarator : to_verilog_parameter_decl (item).declarators ())
47+ declarators.push_back (declarator );
4848
4949 return declarators;
5050}
@@ -173,15 +173,16 @@ void verilog_typecheckt::set_parameter_values(
173173 for (auto &module_item : module_items)
174174 if (module_item.id () == ID_parameter_decl)
175175 {
176- for (auto &decl : to_verilog_parameter_decl (module_item).declarations ())
176+ for (auto &declarator :
177+ to_verilog_parameter_decl (module_item).declarators ())
177178 {
178179 if (p_it!=parameter_values.end ())
179180 {
180181 DATA_INVARIANT (p_it != parameter_values.end (), " have enough parameter values" );
181182
182183 // only overwrite when actually assigned
183184 if (p_it->is_not_nil ())
184- decl .value () = *p_it;
185+ declarator .value () = *p_it;
185186
186187 p_it++;
187188 }
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