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committedNov 27, 2024·
SVA/LTL property instrumentation
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Diff for: ‎CHANGELOG

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use --bmc-with-assumptions to re-enable the previous algorithm.
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* SystemVerilog: streaming concatenation {<<{...}} and {>>{...}}
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* SystemVerilog: set membership operator
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* word-level BMC: LTL/SVA to Buechi with --buechi
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# EBMC 5.3
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