Skip to content

Commit cbf90a4

Browse files
committed
Verilog: KNOWNBUG test for $error
1 parent 4fe66e8 commit cbf90a4

File tree

2 files changed

+17
-0
lines changed

2 files changed

+17
-0
lines changed
Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
KNOWNBUG
2+
error1.v
3+
--module main
4+
^EXIT=0$
5+
^SIGNAL=0$
6+
--
7+
^warning: ignoring
8+
--
9+
This doesn't parse.
Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
module main;
2+
3+
parameter P = 1;
4+
5+
if(P!=1)
6+
$error("something is wrong");
7+
8+
endmodule

0 commit comments

Comments
 (0)